board/samsung/smdk5250/clock_init.c

   1 /*
   2  * Clock setup for SMDK5250 board based on EXYNOS5
   3  *
   4  * Copyright (C) 2012 Samsung Electronics
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <version.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include "setup.h"
  32
  33 void system_clock_init()
  34 {
  35         struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
  36
  37         /*
  38          * MUX_APLL_SEL[0]: FINPLL = 0
  39          * MUX_CPU_SEL[6]: MOUTAPLL = 0
  40          * MUX_HPM_SEL[20]: MOUTAPLL = 0
  41          */
  42         writel(0x0, &clk->src_cpu);
  43
  44         /* MUX_MPLL_SEL[8]: FINPLL = 0 */
  45         writel(0x0, &clk->src_core1);
  46
  47         /*
  48          * VPLLSRC_SEL[0]: FINPLL = 0
  49          * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
  50          */
  51         writel(0x0, &clk->src_top2);
  52
  53         /* MUX_BPLL_SEL[0]: FINPLL = 0 */
  54         writel(0x0, &clk->src_cdrex);
  55
  56         /* MUX_ACLK_* Clock Selection */
  57         writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
  58
  59         /* MUX_ACLK_* Clock Selection */
  60         writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
  61
  62         /* MUX_ACLK_* Clock Selection */
  63         writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
  64
  65         /* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
  66         writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
  67
  68         /* MUX_ATCLK_LEX[0]: ACLK_200 = 0 */
  69         writel(CLK_SRC_LEX_VAL, &clk->src_lex);
  70
  71         /* UART [0-5]: SCLKMPLL = 6 */
  72         writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
  73
  74         /* Set Clock Ratios */
  75         writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
  76
  77         /* Set COPY and HPM Ratio */
  78         writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
  79
  80         /* CORED_RATIO, COREP_RATIO */
  81         writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
  82
  83         /* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
  84         writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
  85
  86         /* ACLK_*_RATIO */
  87         writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
  88
  89         /* ACLK_*_RATIO */
  90         writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
  91
  92         /* CDREX Ratio */
  93         writel(CLK_DIV_CDREX_INIT_VAL, &clk->div_cdrex);
  94
  95         /* MCLK_EFPHY_RATIO[3:0] */
  96         writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2);
  97
  98         /* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
  99         writel(CLK_DIV_LEX_VAL, &clk->div_lex);
 100
 101         /* PCLK_R0X_RATIO[3:0] */
 102         writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
 103
 104         /* PCLK_R1X_RATIO[3:0] */
 105         writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
 106
 107         /* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
 108         writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
 109
 110         /* UART[0-4] */
 111         writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
 112
 113         /* PWM_RATIO[3:0] */
 114         writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
 115
 116         /* SATA_RATIO, USB_DRD_RATIO */
 117         writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
 118
 119         /* MMC[0-1] */
 120         writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
 121
 122         /* MMC[2-3] */
 123         writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
 124
 125         /* MMC[4] */
 126         writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
 127
 128         /* ACLK|PLCK_ACP_RATIO */
 129         writel(CLK_DIV_ACP_VAL, &clk->div_acp);
 130
 131         /* ISPDIV0_RATIO, ISPDIV1_RATIO */
 132         writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
 133
 134         /* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
 135         writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
 136
 137         /* MPWMDIV_RATIO */
 138         writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
 139
 140         /* PLL locktime */
 141         writel(APLL_LOCK_VAL, &clk->apll_lock);
 142
 143         writel(MPLL_LOCK_VAL, &clk->mpll_lock);
 144
 145         writel(BPLL_LOCK_VAL, &clk->bpll_lock);
 146
 147         writel(CPLL_LOCK_VAL, &clk->cpll_lock);
 148
 149         writel(EPLL_LOCK_VAL, &clk->epll_lock);
 150
 151         writel(VPLL_LOCK_VAL, &clk->vpll_lock);
 152
 153         sdelay(0x10000);
 154
 155         /* Set APLL */
 156         writel(APLL_CON1_VAL, &clk->apll_con1);
 157         writel(APLL_CON0_VAL, &clk->apll_con0);
 158         sdelay(0x30000);
 159
 160         /* Set MPLL */
 161         writel(MPLL_CON1_VAL, &clk->mpll_con1);
 162         writel(MPLL_CON0_VAL, &clk->mpll_con0);
 163         sdelay(0x30000);
 164         writel(BPLL_CON1_VAL, &clk->bpll_con1);
 165         writel(BPLL_CON0_VAL, &clk->bpll_con0);
 166         sdelay(0x30000);
 167
 168         /* Set CPLL */
 169         writel(CPLL_CON1_VAL, &clk->cpll_con1);
 170         writel(CPLL_CON0_VAL, &clk->cpll_con0);
 171         sdelay(0x30000);
 172
 173         /* Set EPLL */
 174         writel(EPLL_CON2_VAL, &clk->epll_con2);
 175         writel(EPLL_CON1_VAL, &clk->epll_con1);
 176         writel(EPLL_CON0_VAL, &clk->epll_con0);
 177         sdelay(0x30000);
 178
 179         /* Set VPLL */
 180         writel(VPLL_CON2_VAL, &clk->vpll_con2);
 181         writel(VPLL_CON1_VAL, &clk->vpll_con1);
 182         writel(VPLL_CON0_VAL, &clk->vpll_con0);
 183         sdelay(0x30000);
 184
 185         /* Set MPLL */
 186         /* After Initiallising th PLL select the sources accordingly */
 187         /* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
 188         writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
 189
 190         /* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
 191         writel(CLK_SRC_CORE1_VAL, &clk->src_core1);
 192
 193         /* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
 194         writel(CLK_SRC_CDREX_INIT_VAL, &clk->src_cdrex);
 195
 196         /*
 197          * VPLLSRC_SEL[0]: FINPLL = 0
 198          * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
 199          * MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
 200          */
 201         writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
 202 }