2 * Machine Specific Values for ORIGEN board based on S5PV310
4 * Copyright (C) 2011 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _ORIGEN_SETUP_H
26 #define _ORIGEN_SETUP_H
30 #include <asm/arch/cpu.h>
32 /* Offsets of clock registers (sources and dividers) */
33 #define CLK_SRC_CPU_OFFSET 0x14200
34 #define CLK_DIV_CPU0_OFFSET 0x14500
35 #define CLK_DIV_CPU1_OFFSET 0x14504
37 #define CLK_SRC_DMC_OFFSET 0x10200
38 #define CLK_DIV_DMC0_OFFSET 0x10500
39 #define CLK_DIV_DMC1_OFFSET 0x10504
41 #define CLK_SRC_TOP0_OFFSET 0xC210
42 #define CLK_SRC_TOP1_OFFSET 0xC214
43 #define CLK_DIV_TOP_OFFSET 0xC510
45 #define CLK_SRC_LEFTBUS_OFFSET 0x4200
46 #define CLK_DIV_LEFTBUS_OFFSET 0x4500
48 #define CLK_SRC_RIGHTBUS_OFFSET 0x8200
49 #define CLK_DIV_RIGHTBUS_OFFSET 0x8500
51 #define CLK_SRC_FSYS_OFFSET 0xC240
52 #define CLK_DIV_FSYS1_OFFSET 0xC544
53 #define CLK_DIV_FSYS2_OFFSET 0xC548
54 #define CLK_DIV_FSYS3_OFFSET 0xC54C
56 #define CLK_SRC_CAM_OFFSET 0xC220
57 #define CLK_SRC_TV_OFFSET 0xC224
58 #define CLK_SRC_MFC_OFFSET 0xC228
59 #define CLK_SRC_G3D_OFFSET 0xC22C
60 #define CLK_SRC_LCD0_OFFSET 0xC234
61 #define CLK_SRC_PERIL0_OFFSET 0xC250
63 #define CLK_DIV_CAM_OFFSET 0xC520
64 #define CLK_DIV_TV_OFFSET 0xC524
65 #define CLK_DIV_MFC_OFFSET 0xC528
66 #define CLK_DIV_G3D_OFFSET 0xC52C
67 #define CLK_DIV_LCD0_OFFSET 0xC534
68 #define CLK_DIV_PERIL0_OFFSET 0xC550
70 #define CLK_SRC_LCD0_OFFSET 0xC234
72 #define APLL_LOCK_OFFSET 0x14000
73 #define MPLL_LOCK_OFFSET 0x14008
74 #define APLL_CON0_OFFSET 0x14100
75 #define APLL_CON1_OFFSET 0x14104
76 #define MPLL_CON0_OFFSET 0x14108
77 #define MPLL_CON1_OFFSET 0x1410C
79 #define EPLL_LOCK_OFFSET 0xC010
80 #define VPLL_LOCK_OFFSET 0xC020
81 #define EPLL_CON0_OFFSET 0xC110
82 #define EPLL_CON1_OFFSET 0xC114
83 #define VPLL_CON0_OFFSET 0xC120
84 #define VPLL_CON1_OFFSET 0xC124
86 /* DMC: DRAM Controllor Register offsets */
87 #define DMC_CONCONTROL 0x00
88 #define DMC_MEMCONTROL 0x04
89 #define DMC_MEMCONFIG0 0x08
90 #define DMC_MEMCONFIG1 0x0C
91 #define DMC_DIRECTCMD 0x10
92 #define DMC_PRECHCONFIG 0x14
93 #define DMC_PHYCONTROL0 0x18
94 #define DMC_PHYCONTROL1 0x1C
95 #define DMC_PHYCONTROL2 0x20
96 #define DMC_TIMINGAREF 0x30
97 #define DMC_TIMINGROW 0x34
98 #define DMC_TIMINGDATA 0x38
99 #define DMC_TIMINGPOWER 0x3C
100 #define DMC_PHYZQCONTROL 0x44
102 /* Bus Configuration Register Address */
103 #define ASYNC_CONFIG 0x10010350
105 /* MIU Config Register Offsets*/
106 #define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
107 #define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
109 /* Offset for inform registers */
110 #define INFORM0_OFFSET 0x800
111 #define INFORM1_OFFSET 0x804
113 /* GPIO Offsets for UART: GPIO Contol Register */
114 #define EXYNOS4_GPIO_A0_CON_OFFSET 0x00
115 #define EXYNOS4_GPIO_A1_CON_OFFSET 0x20
117 /* UART Register offsets */
118 #define ULCON_OFFSET 0x00
119 #define UCON_OFFSET 0x04
120 #define UFCON_OFFSET 0x08
121 #define UBRDIV_OFFSET 0x28
122 #define UFRACVAL_OFFSET 0x2C
125 #define MUX_HPM_SEL_MOUTAPLL 0x0
126 #define MUX_HPM_SEL_SCLKMPLL 0x1
127 #define MUX_CORE_SEL_MOUTAPLL 0x0
128 #define MUX_CORE_SEL_SCLKMPLL 0x1
129 #define MUX_MPLL_SEL_FILPLL 0x0
130 #define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
131 #define MUX_APLL_SEL_FILPLL 0x0
132 #define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
133 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
134 | (MUX_CORE_SEL_MOUTAPLL << 16) \
135 | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
136 | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
139 #define APLL_RATIO 0x0
140 #define PCLK_DBG_RATIO 0x1
141 #define ATB_RATIO 0x3
142 #define PERIPH_RATIO 0x3
143 #define COREM1_RATIO 0x7
144 #define COREM0_RATIO 0x3
145 #define CORE_RATIO 0x0
146 #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
147 | (PCLK_DBG_RATIO << 20) \
148 | (ATB_RATIO << 16) \
149 | (PERIPH_RATIO << 12) \
150 | (COREM1_RATIO << 8) \
151 | (COREM0_RATIO << 4) \
155 #define HPM_RATIO 0x0
156 #define COPY_RATIO 0x3
157 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
160 #define MUX_PWI_SEL_XXTI 0x0
161 #define MUX_PWI_SEL_XUSBXTI 0x1
162 #define MUX_PWI_SEL_SCLK_HDMI24M 0x2
163 #define MUX_PWI_SEL_SCLK_USBPHY0 0x3
164 #define MUX_PWI_SEL_SCLK_USBPHY1 0x4
165 #define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
166 #define MUX_PWI_SEL_SCLKMPLL 0x6
167 #define MUX_PWI_SEL_SCLKEPLL 0x7
168 #define MUX_PWI_SEL_SCLKVPLL 0x8
169 #define MUX_DPHY_SEL_SCLKMPLL 0x0
170 #define MUX_DPHY_SEL_SCLKAPLL 0x1
171 #define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
172 #define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
173 #define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
174 | (MUX_DPHY_SEL_SCLKMPLL << 8) \
175 | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
178 #define CORE_TIMERS_RATIO 0x1
179 #define COPY2_RATIO 0x3
180 #define DMCP_RATIO 0x1
181 #define DMCD_RATIO 0x1
182 #define DMC_RATIO 0x1
183 #define DPHY_RATIO 0x1
184 #define ACP_PCLK_RATIO 0x1
185 #define ACP_RATIO 0x3
186 #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
187 | (COPY2_RATIO << 24) \
188 | (DMCP_RATIO << 20) \
189 | (DMCD_RATIO << 16) \
190 | (DMC_RATIO << 12) \
191 | (DPHY_RATIO << 8) \
192 | (ACP_PCLK_RATIO << 4) \
196 #define DPM_RATIO 0x1
197 #define DVSEM_RATIO 0x1
198 #define PWI_RATIO 0x1
199 #define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
200 | (DVSEM_RATIO << 16) \
204 #define MUX_ONENAND_SEL_ACLK_133 0x0
205 #define MUX_ONENAND_SEL_ACLK_160 0x1
206 #define MUX_ACLK_133_SEL_SCLKMPLL 0x0
207 #define MUX_ACLK_133_SEL_SCLKAPLL 0x1
208 #define MUX_ACLK_160_SEL_SCLKMPLL 0x0
209 #define MUX_ACLK_160_SEL_SCLKAPLL 0x1
210 #define MUX_ACLK_100_SEL_SCLKMPLL 0x0
211 #define MUX_ACLK_100_SEL_SCLKAPLL 0x1
212 #define MUX_ACLK_200_SEL_SCLKMPLL 0x0
213 #define MUX_ACLK_200_SEL_SCLKAPLL 0x1
214 #define MUX_VPLL_SEL_FINPLL 0x0
215 #define MUX_VPLL_SEL_FOUTVPLL 0x1
216 #define MUX_EPLL_SEL_FINPLL 0x0
217 #define MUX_EPLL_SEL_FOUTEPLL 0x1
218 #define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
219 #define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
220 #define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
221 | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
222 | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
223 | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
224 | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
225 | (MUX_VPLL_SEL_FINPLL << 8) \
226 | (MUX_EPLL_SEL_FINPLL << 4)\
227 | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
230 #define VPLLSRC_SEL_FINPLL 0x0
231 #define VPLLSRC_SEL_SCLKHDMI24M 0x1
232 #define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
235 #define ONENAND_RATIO 0x0
236 #define ACLK_133_RATIO 0x5
237 #define ACLK_160_RATIO 0x4
238 #define ACLK_100_RATIO 0x7
239 #define ACLK_200_RATIO 0x3
240 #define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
241 | (ACLK_133_RATIO << 12)\
242 | (ACLK_160_RATIO << 8) \
243 | (ACLK_100_RATIO << 4) \
244 | (ACLK_200_RATIO << 0))
246 /* CLK_SRC_LEFTBUS */
247 #define MUX_GDL_SEL_SCLKMPLL 0x0
248 #define MUX_GDL_SEL_SCLKAPLL 0x1
249 #define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
251 /* CLK_DIV_LEFTBUS */
252 #define GPL_RATIO 0x1
253 #define GDL_RATIO 0x3
254 #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
256 /* CLK_SRC_RIGHTBUS */
257 #define MUX_GDR_SEL_SCLKMPLL 0x0
258 #define MUX_GDR_SEL_SCLKAPLL 0x1
259 #define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
261 /* CLK_DIV_RIGHTBUS */
262 #define GPR_RATIO 0x1
263 #define GDR_RATIO 0x3
264 #define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
266 /* CLK_SRS_FSYS: 6 = SCLKMPLL */
267 #define SATA_SEL_SCLKMPLL 0
268 #define SATA_SEL_SCLKAPLL 1
270 #define MMC_SEL_XXTI 0
271 #define MMC_SEL_XUSBXTI 1
272 #define MMC_SEL_SCLK_HDMI24M 2
273 #define MMC_SEL_SCLK_USBPHY0 3
274 #define MMC_SEL_SCLK_USBPHY1 4
275 #define MMC_SEL_SCLK_HDMIPHY 5
276 #define MMC_SEL_SCLKMPLL 6
277 #define MMC_SEL_SCLKEPLL 7
278 #define MMC_SEL_SCLKVPLL 8
280 #define MMCC0_SEL MMC_SEL_SCLKMPLL
281 #define MMCC1_SEL MMC_SEL_SCLKMPLL
282 #define MMCC2_SEL MMC_SEL_SCLKMPLL
283 #define MMCC3_SEL MMC_SEL_SCLKMPLL
284 #define MMCC4_SEL MMC_SEL_SCLKMPLL
285 #define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
286 | (MMCC4_SEL << 16) \
287 | (MMCC3_SEL << 12) \
292 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
294 #define MMC0_RATIO 0xF
295 #define MMC0_PRE_RATIO 0x0
296 #define MMC1_RATIO 0xF
297 #define MMC1_PRE_RATIO 0x0
298 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
299 | (MMC1_RATIO << 16) \
300 | (MMC0_PRE_RATIO << 8) \
304 #define MMC2_RATIO 0xF
305 #define MMC2_PRE_RATIO 0x0
306 #define MMC3_RATIO 0xF
307 #define MMC3_PRE_RATIO 0x0
308 #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
309 | (MMC3_RATIO << 16) \
310 | (MMC2_PRE_RATIO << 8) \
314 #define MMC4_RATIO 0xF
315 #define MMC4_PRE_RATIO 0x0
316 #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
320 #define UART_SEL_XXTI 0
321 #define UART_SEL_XUSBXTI 1
322 #define UART_SEL_SCLK_HDMI24M 2
323 #define UART_SEL_SCLK_USBPHY0 3
324 #define UART_SEL_SCLK_USBPHY1 4
325 #define UART_SEL_SCLK_HDMIPHY 5
326 #define UART_SEL_SCLKMPLL 6
327 #define UART_SEL_SCLKEPLL 7
328 #define UART_SEL_SCLKVPLL 8
330 #define UART0_SEL UART_SEL_SCLKMPLL
331 #define UART1_SEL UART_SEL_SCLKMPLL
332 #define UART2_SEL UART_SEL_SCLKMPLL
333 #define UART3_SEL UART_SEL_SCLKMPLL
334 #define UART4_SEL UART_SEL_SCLKMPLL
335 #define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
336 | (UART3_SEL << 12) \
341 /* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
343 #define UART0_RATIO 7
344 #define UART1_RATIO 7
345 #define UART2_RATIO 7
346 #define UART3_RATIO 7
347 #define UART4_RATIO 7
348 #define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
349 | (UART3_RATIO << 12) \
350 | (UART2_RATIO << 8) \
351 | (UART1_RATIO << 4) \
352 | (UART0_RATIO << 0))
354 /* Clock Source CAM/FIMC */
356 #define CAM0_SEL_XUSBXTI 1
357 #define CAM1_SEL_XUSBXTI 1
358 #define CSIS0_SEL_XUSBXTI 1
359 #define CSIS1_SEL_XUSBXTI 1
361 #define FIMC_SEL_SCLKMPLL 6
362 #define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
363 #define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
364 #define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
365 #define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
367 #define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
368 | (CSIS0_SEL_XUSBXTI << 24) \
369 | (CAM1_SEL_XUSBXTI << 20) \
370 | (CAM0_SEL_XUSBXTI << 16) \
371 | (FIMC3_LCLK_SEL << 12) \
372 | (FIMC2_LCLK_SEL << 8) \
373 | (FIMC1_LCLK_SEL << 4) \
374 | (FIMC0_LCLK_SEL << 0))
378 #define FIMC0_LCLK_RATIO 4
379 #define FIMC1_LCLK_RATIO 4
380 #define FIMC2_LCLK_RATIO 4
381 #define FIMC3_LCLK_RATIO 4
382 #define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
383 | (FIMC2_LCLK_RATIO << 8) \
384 | (FIMC1_LCLK_RATIO << 4) \
385 | (FIMC0_LCLK_RATIO << 0))
389 #define MFC_SEL_MPLL 0
391 #define MFC_SEL MOUTMFC_0
392 #define MFC_0_SEL MFC_SEL_MPLL
393 #define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
398 #define CLK_DIV_MFC_VAL (MFC_RATIO)
402 #define G3D_SEL_MPLL 0
404 #define G3D_SEL MOUTG3D_0
405 #define G3D_0_SEL G3D_SEL_MPLL
406 #define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
410 #define CLK_DIV_G3D_VAL (G3D_RATIO)
414 #define FIMD_SEL_SCLKMPLL 6
415 #define MDNIE0_SEL_XUSBXTI 1
416 #define MDNIE_PWM0_SEL_XUSBXTI 1
417 #define MIPI0_SEL_XUSBXTI 1
418 #define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
419 | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
420 | (MDNIE0_SEL_XUSBXTI << 4) \
421 | (FIMD_SEL_SCLKMPLL << 0))
424 #define FIMD0_RATIO 4
425 #define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
427 /* Required period to generate a stable clock output */
429 #define PLL_LOCKTIME 0x1C20
434 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
440 #define APLL_MDIV 0xFA
441 #define APLL_PDIV 0x6
442 #define APLL_SDIV 0x1
443 #define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
446 #define APLL_AFC_ENB 0x1
448 #define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
451 #define MPLL_MDIV 0xC8
452 #define MPLL_PDIV 0x6
453 #define MPLL_SDIV 0x1
454 #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
457 #define MPLL_AFC_ENB 0x0
458 #define MPLL_AFC 0x1C
459 #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
462 #define EPLL_MDIV 0x30
463 #define EPLL_PDIV 0x3
464 #define EPLL_SDIV 0x2
465 #define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
469 #define EPLL_CON1_VAL (EPLL_K >> 0)
472 #define VPLL_MDIV 0x35
473 #define VPLL_PDIV 0x3
474 #define VPLL_SDIV 0x2
475 #define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
478 #define VPLL_SSCG_EN DISABLE
479 #define VPLL_SEL_PF_DN_SPREAD 0x0
480 #define VPLL_MRR 0x11
483 #define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
484 | (VPLL_SEL_PF_DN_SPREAD << 29) \
489 * UART GPIO_A0/GPIO_A1 Control Register Value
492 #define EXYNOS4_GPIO_A0_CON_VAL 0x22222222
493 #define EXYNOS4_GPIO_A1_CON_VAL 0x222222
495 /* ULCON: UART Line Control Value 8N1 */
496 #define WORD_LEN_5_BIT 0x00
497 #define WORD_LEN_6_BIT 0x01
498 #define WORD_LEN_7_BIT 0x02
499 #define WORD_LEN_8_BIT 0x03
501 #define STOP_BIT_1 0x00
502 #define STOP_BIT_2 0x01
504 #define NO_PARITY 0x00
505 #define ODD_PARITY 0x4
506 #define EVEN_PARITY 0x5
507 #define FORCED_PARITY_CHECK_AS_1 0x6
508 #define FORCED_PARITY_CHECK_AS_0 0x7
510 #define INFRAMODE_NORMAL 0x00
511 #define INFRAMODE_INFRARED 0x01
513 #define ULCON_VAL ((INFRAMODE_NORMAL << 6) \
515 | (STOP_BIT_1 << 2) \
516 | (WORD_LEN_8_BIT << 0))
519 * UCON: UART Control Value
520 * Tx_interrupt Type: Level
521 * Rx_interrupt Type: Level
522 * Rx Timeout Enabled: Yes
523 * Rx-Error Atatus_Int Enable: Yes
526 * Transmit mode : Interrupt request/polling
527 * Receive mode : Interrupt request/polling
529 #define TX_PULSE_INTERRUPT 0
530 #define TX_LEVEL_INTERRUPT 1
531 #define RX_PULSE_INTERRUPT 0
532 #define RX_LEVEL_INTERRUPT 1
534 #define RX_TIME_OUT ENABLE
535 #define RX_ERROR_STATE_INT_ENB ENABLE
536 #define LOOP_BACK DISABLE
537 #define BREAK_SIGNAL DISABLE
539 #define TX_MODE_DISABLED 0X00
540 #define TX_MODE_IRQ_OR_POLL 0X01
541 #define TX_MODE_DMA 0X02
543 #define RX_MODE_DISABLED 0X00
544 #define RX_MODE_IRQ_OR_POLL 0X01
545 #define RX_MODE_DMA 0X02
547 #define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \
548 | (RX_LEVEL_INTERRUPT << 8) \
549 | (RX_TIME_OUT << 7) \
550 | (RX_ERROR_STATE_INT_ENB << 6) \
552 | (BREAK_SIGNAL << 4) \
553 | (TX_MODE_IRQ_OR_POLL << 2) \
554 | (RX_MODE_IRQ_OR_POLL << 0))
557 * UFCON: UART FIFO Control Value
558 * Tx FIFO Trigger LEVEL: 2 Bytes (001)
559 * Rx FIFO Trigger LEVEL: 2 Bytes (001)
564 #define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00
565 #define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1
566 #define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2
567 #define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3
568 #define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4
569 #define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5
570 #define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6
571 #define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7
573 #define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0
574 #define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1
575 #define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2
576 #define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3
577 #define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4
578 #define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5
579 #define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6
580 #define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7
582 #define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES
583 #define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES
584 #define TX_FIFO_RESET DISABLE
585 #define RX_FIFO_RESET DISABLE
586 #define FIFO_ENABLE ENABLE
587 #define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \
588 | (RX_FIFO_TRIGGER_LEVEL << 4) \
589 | (TX_FIFO_RESET << 2) \
590 | (RX_FIFO_RESET << 1) \
591 | (FIFO_ENABLE << 0))
593 * Baud Rate Division Value
595 * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
596 * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
598 #define UBRDIV_VAL 0x35
601 * Fractional Part of Baud Rate Divisor:
603 * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
604 * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
606 #define UFRACVAL_VAL 0x4