1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2021 Google LLC
6 #define LOG_CATEGORY UCLASS_ETH
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch/sromc.h>
23 FDT_SROM_TIMING_COUNT,
26 static int exyno5_sromc_probe(struct udevice *dev)
28 u32 timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
29 u32 smc_bw_conf, smc_bc_conf;
30 int bank; /* srom bank number */
31 int width; /* bus width in bytes */
34 if (!IS_ENABLED(CONFIG_SMC911X))
37 bank = dev_read_s32_default(dev, "bank", 0);
38 width = dev_read_s32_default(dev, "width", 2);
40 /* Ethernet needs data bus width of 16 bits */
42 log_debug("Unsupported bus width %d\n", width);
43 return log_msg_ret("width", -EINVAL);
45 ret = dev_read_u32_array(dev, "srom-timing", timing,
46 FDT_SROM_TIMING_COUNT);
48 return log_msg_ret("sromc", -EINVAL);
50 smc_bw_conf = SROMC_DATA16_WIDTH(bank) | SROMC_BYTE_ENABLE(bank);
51 smc_bc_conf = SROMC_BC_TACS(timing[FDT_SROM_TACS]) |
52 SROMC_BC_TCOS(timing[FDT_SROM_TCOS]) |
53 SROMC_BC_TACC(timing[FDT_SROM_TACC]) |
54 SROMC_BC_TCOH(timing[FDT_SROM_TCOH]) |
55 SROMC_BC_TAH(timing[FDT_SROM_TAH]) |
56 SROMC_BC_TACP(timing[FDT_SROM_TACP]) |
57 SROMC_BC_PMC(timing[FDT_SROM_PMC]);
59 /* Select and configure the SROMC bank */
60 exynos_pinmux_config(PERIPH_ID_SROMC, bank);
61 s5p_config_sromc(bank, smc_bw_conf, smc_bc_conf);
66 static const struct udevice_id exyno5_sromc_ids[] = {
67 { .compatible = "samsung,exynos5-sromc" },
71 U_BOOT_DRIVER(exyno5_sromc) = {
72 .name = "exyno5_sromc",
73 .id = UCLASS_SIMPLE_BUS,
74 .of_match = exyno5_sromc_ids,
75 .probe = exyno5_sromc_probe,