board/ronetix/pm9g45/pm9g45.c

   1 /*
   2  * (C) Copyright 2010
   3  * Ilko Iliev <iliev@ronetix.at>
   4  * Asen Dimov <dimov@ronetix.at>
   5  * Ronetix GmbH <www.ronetix.at>
   6  *
   7  * (C) Copyright 2007-2008
   8  * Stelian Pop <stelian@popies.net>
   9  * Lead Tech Design <www.leadtechdesign.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <linux/sizes.h>
  16 #include <asm/io.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/at91sam9_smc.h>
  19 #include <asm/arch/at91_common.h>
  20 #include <asm/arch/at91_rstc.h>
  21 #include <asm/arch/at91_matrix.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/clk.h>
  24 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  25 #include <net.h>
  26 #endif
  27 #include <netdev.h>
  28 #include <asm/mach-types.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 /*
  33  * Miscelaneous platform dependent initialisations
  34  */
  35
  36 #ifdef CONFIG_CMD_NAND
  37 static void pm9g45_nand_hw_init(void)
  38 {
  39         unsigned long csa;
  40         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  41         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  42
  43         /* Enable CS3 */
  44         csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
  45         writel(csa, &matrix->ccr[6]);
  46
  47         /* Configure SMC CS3 for NAND/SmartMedia */
  48         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  49                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  50                 &smc->cs[3].setup);
  51
  52         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
  53                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
  54                 &smc->cs[3].pulse);
  55
  56         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
  57                 &smc->cs[3].cycle);
  58
  59         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  60                 AT91_SMC_MODE_EXNW_DISABLE |
  61                 AT91_SMC_MODE_DBW_8 |
  62                 AT91_SMC_MODE_TDF_CYCLE(3),
  63                 &smc->cs[3].mode);
  64
  65         at91_periph_clk_enable(ATMEL_ID_PIOC);
  66
  67 #ifdef CONFIG_SYS_NAND_READY_PIN
  68         /* Configure RDY/BSY */
  69         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  70 #endif
  71
  72         /* Enable NandFlash */
  73         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  74 }
  75 #endif
  76
  77 #ifdef CONFIG_MACB
  78 static void pm9g45_macb_hw_init(void)
  79 {
  80         /*
  81          * PD2 enables the 50MHz oscillator for Ethernet PHY
  82          * 1 - enable
  83          * 0 - disable
  84          */
  85         at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
  86         at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
  87
  88         at91_periph_clk_enable(ATMEL_ID_EMAC);
  89
  90         /*
  91          * Disable pull-up on:
  92          *      RXDV (PA15) => PHY normal mode (not Test mode)
  93          *      ERX0 (PA12) => PHY ADDR0
  94          *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
  95          *
  96          * PHY has internal pull-down
  97          */
  98         at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
  99         at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
 100         at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
 101
 102         /* Re-enable pull-up */
 103         at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
 104         at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
 105         at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
 106
 107         at91_macb_hw_init();
 108 }
 109 #endif
 110
 111 int board_early_init_f(void)
 112 {
 113         at91_periph_clk_enable(ATMEL_ID_PIOA);
 114         at91_periph_clk_enable(ATMEL_ID_PIOB);
 115         at91_periph_clk_enable(ATMEL_ID_PIOC);
 116         at91_periph_clk_enable(ATMEL_ID_PIODE);
 117
 118         at91_seriald_hw_init();
 119
 120         return 0;
 121 }
 122
 123 int board_init(void)
 124 {
 125         /* arch number of AT91SAM9M10G45EK-Board */
 126         gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
 127         /* adress of boot parameters */
 128         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 129
 130 #ifdef CONFIG_CMD_NAND
 131         pm9g45_nand_hw_init();
 132 #endif
 133
 134 #ifdef CONFIG_MACB
 135         pm9g45_macb_hw_init();
 136 #endif
 137         return 0;
 138 }
 139
 140 int dram_init(void)
 141 {
 142         /* dram_init must store complete ramsize in gd->ram_size */
 143         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 144                                 PHYS_SDRAM_SIZE);
 145         return 0;
 146 }
 147
 148 int dram_init_banksize(void)
 149 {
 150         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 151         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 152
 153         return 0;
 154 }
 155
 156 #ifdef CONFIG_RESET_PHY_R
 157 void reset_phy(void)
 158 {
 159 #ifdef CONFIG_MACB
 160         /*
 161          * Initialize ethernet HW addr prior to starting Linux,
 162          * needed for nfsroot
 163          */
 164         eth_init();
 165 #endif
 166 }
 167 #endif
 168
 169 int board_eth_init(bd_t *bis)
 170 {
 171         int rc = 0;
 172 #ifdef CONFIG_MACB
 173         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
 174 #endif
 175         return rc;
 176 }