board/ronetix/pm9263/pm9263.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
   7  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   8  */
   9
  10 #include <common.h>
  11 #include <init.h>
  12 #include <linux/sizes.h>
  13 #include <asm/io.h>
  14 #include <asm/gpio.h>
  15 #include <asm/arch/at91sam9_smc.h>
  16 #include <asm/arch/at91_common.h>
  17 #include <asm/arch/at91_rstc.h>
  18 #include <asm/arch/at91_matrix.h>
  19 #include <asm/arch/clk.h>
  20 #include <asm/arch/gpio.h>
  21 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  22 #include <net.h>
  23 #endif
  24 #include <netdev.h>
  25 #include <asm/mach-types.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /* ------------------------------------------------------------------------- */
  30 /*
  31  * Miscelaneous platform dependent initialisations
  32  */
  33
  34 #ifdef CONFIG_CMD_NAND
  35 static void pm9263_nand_hw_init(void)
  36 {
  37         unsigned long csa;
  38         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
  39         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  40
  41         /* Enable CS3 */
  42         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  43         writel(csa, &matrix->csa[0]);
  44
  45         /* Configure SMC CS3 for NAND/SmartMedia */
  46         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  47                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  48                 &smc->cs[3].setup);
  49
  50         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  51                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  52                 &smc->cs[3].pulse);
  53
  54         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  55                 &smc->cs[3].cycle);
  56
  57         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  58                 AT91_SMC_MODE_EXNW_DISABLE |
  59 #ifdef CONFIG_SYS_NAND_DBW_16
  60                 AT91_SMC_MODE_DBW_16 |
  61 #else /* CONFIG_SYS_NAND_DBW_8 */
  62                 AT91_SMC_MODE_DBW_8 |
  63 #endif
  64                 AT91_SMC_MODE_TDF_CYCLE(2),
  65                 &smc->cs[3].mode);
  66
  67         /* Configure RDY/BSY */
  68         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  69
  70         /* Enable NandFlash */
  71         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  72 }
  73 #endif
  74
  75 #ifdef CONFIG_MACB
  76 static void pm9263_macb_hw_init(void)
  77 {
  78         /*
  79          * PB27 enables the 50MHz oscillator for Ethernet PHY
  80          * 1 - enable
  81          * 0 - disable
  82          */
  83         at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
  84         at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
  85
  86         at91_periph_clk_enable(ATMEL_ID_EMAC);
  87
  88         /*
  89          * Disable pull-up on:
  90          *      RXDV (PC25) => PHY normal mode (not Test mode)
  91          *      ERX0 (PE25) => PHY ADDR0
  92          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  93          *
  94          * PHY has internal pull-down
  95          */
  96
  97         at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
  98         at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
  99         at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
 100
 101         /* Re-enable pull-up */
 102         at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
 103         at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
 104         at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
 105
 106         at91_macb_hw_init();
 107 }
 108 #endif
 109
 110 #ifdef CONFIG_LCD
 111
 112 #ifdef CONFIG_LCD_IN_PSRAM
 113
 114 #define PSRAM_CRE_PIN   AT91_PIO_PORTB, 29
 115 #define PSRAM_CTRL_REG  (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
 116
 117 /* Initialize the PSRAM memory */
 118 static int pm9263_lcd_hw_psram_init(void)
 119 {
 120         unsigned long csa;
 121         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
 122         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 123
 124         /* Enable CS3  3.3v, no pull-ups */
 125         csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
 126                 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
 127
 128         writel(csa, &matrix->csa[1]);
 129
 130         /* Configure SMC1 CS0 for PSRAM - 16-bit */
 131         writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
 132                 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
 133                 &smc->cs[0].setup);
 134
 135         writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
 136                 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
 137                 &smc->cs[0].pulse);
 138
 139         writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
 140                 &smc->cs[0].cycle);
 141
 142         writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
 143                 &smc->cs[0].mode);
 144
 145         /* setup PB29 as output */
 146         at91_set_pio_output(PSRAM_CRE_PIN, 1);
 147
 148         at91_set_pio_value(PSRAM_CRE_PIN, 0);   /* set PSRAM_CRE_PIN to '0' */
 149
 150         /* PSRAM: write BCR */
 151         readw(PSRAM_CTRL_REG);
 152         readw(PSRAM_CTRL_REG);
 153         writew(1, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 154         writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
 155
 156         /* write RCR of the PSRAM */
 157         readw(PSRAM_CTRL_REG);
 158         readw(PSRAM_CTRL_REG);
 159         writew(0, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 160         /* set RCR; 0x10-async mode,0x90-page mode */
 161         writew(0x90, PSRAM_CTRL_REG);
 162
 163         /*
 164          * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
 165          * MT45W2M16B - CRE must be 0
 166          * MT45W2M16A - CRE must be 1
 167          */
 168         writew(0x1234, PHYS_PSRAM);
 169         writew(0x5678, PHYS_PSRAM + 2);
 170
 171         /* test if the chip is MT45W2M16B */
 172         if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
 173                 /* try with CRE=1 (MT45W2M16A) */
 174                 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
 175
 176                 /* write RCR of the PSRAM */
 177                 readw(PSRAM_CTRL_REG);
 178                 readw(PSRAM_CTRL_REG);
 179                 writew(0, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 180                 /* set RCR;0x10-async mode,0x90-page mode */
 181                 writew(0x90, PSRAM_CTRL_REG);
 182
 183
 184                 writew(0x1234, PHYS_PSRAM);
 185                 writew(0x5678, PHYS_PSRAM+2);
 186                 if ((readw(PHYS_PSRAM) != 0x1234)
 187                   || (readw(PHYS_PSRAM + 2) != 0x5678))
 188                         return 1;
 189
 190         }
 191
 192         /* Bus matrix */
 193         writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
 194         writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
 195
 196         return 0;
 197 }
 198 #endif
 199
 200 static void pm9263_lcd_hw_init(void)
 201 {
 202         /* Power Control */
 203         at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
 204         at91_set_pio_value(AT91_PIO_PORTA, 22, 0);      /* power down */
 205
 206 #ifdef CONFIG_LCD_IN_PSRAM
 207         /* initialize te PSRAM */
 208         int stat = pm9263_lcd_hw_psram_init();
 209
 210         gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
 211 #else
 212         gd->fb_base = ATMEL_BASE_SRAM0;
 213 #endif
 214
 215 }
 216
 217 #endif /* CONFIG_LCD */
 218
 219 int board_early_init_f(void)
 220 {
 221         return 0;
 222 }
 223
 224 int board_init(void)
 225 {
 226         /* arch number of AT91SAM9263EK-Board */
 227         gd->bd->bi_arch_number = MACH_TYPE_PM9263;
 228
 229         /* adress of boot parameters */
 230         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 231
 232 #ifdef CONFIG_CMD_NAND
 233         pm9263_nand_hw_init();
 234 #endif
 235 #ifdef CONFIG_MACB
 236         pm9263_macb_hw_init();
 237 #endif
 238 #ifdef CONFIG_USB_OHCI_NEW
 239         at91_uhp_hw_init();
 240 #endif
 241 #ifdef CONFIG_LCD
 242         pm9263_lcd_hw_init();
 243 #endif
 244         return 0;
 245 }
 246
 247 int dram_init(void)
 248 {
 249         /* dram_init must store complete ramsize in gd->ram_size */
 250         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 251                                 PHYS_SDRAM_SIZE);
 252         return 0;
 253 }
 254
 255 int dram_init_banksize(void)
 256 {
 257         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 258         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 259
 260         return 0;
 261 }
 262
 263 #ifdef CONFIG_RESET_PHY_R
 264 void reset_phy(void)
 265 {
 266 }
 267 #endif
 268
 269 int board_eth_init(bd_t *bis)
 270 {
 271         int rc = 0;
 272 #ifdef CONFIG_MACB
 273         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
 274 #endif
 275         return rc;
 276 }
 277
 278 #ifdef CONFIG_DISPLAY_BOARDINFO
 279 int checkboard (void)
 280 {
 281         char *ss;
 282
 283         printf ("Board : Ronetix PM9263\n");
 284
 285         switch (gd->fb_base) {
 286         case PHYS_PSRAM:
 287                 ss = "(PSRAM)";
 288                 break;
 289
 290         case ATMEL_BASE_SRAM0:
 291                 ss = "(Internal SRAM)";
 292                 break;
 293
 294         default:
 295                 ss = "";
 296                 break;
 297         }
 298         printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
 299
 300         printf ("\n");
 301         return 0;
 302 }
 303 #endif