board/ronetix/pm9263/pm9263.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
   7  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   8  */
   9
  10 #include <common.h>
  11 #include <linux/sizes.h>
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <asm/arch/at91sam9_smc.h>
  15 #include <asm/arch/at91_common.h>
  16 #include <asm/arch/at91_rstc.h>
  17 #include <asm/arch/at91_matrix.h>
  18 #include <asm/arch/clk.h>
  19 #include <asm/arch/gpio.h>
  20 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  21 #include <net.h>
  22 #endif
  23 #include <netdev.h>
  24 #include <asm/mach-types.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 /* ------------------------------------------------------------------------- */
  29 /*
  30  * Miscelaneous platform dependent initialisations
  31  */
  32
  33 #ifdef CONFIG_CMD_NAND
  34 static void pm9263_nand_hw_init(void)
  35 {
  36         unsigned long csa;
  37         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
  38         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  39
  40         /* Enable CS3 */
  41         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  42         writel(csa, &matrix->csa[0]);
  43
  44         /* Configure SMC CS3 for NAND/SmartMedia */
  45         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  46                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  47                 &smc->cs[3].setup);
  48
  49         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  50                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  51                 &smc->cs[3].pulse);
  52
  53         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  54                 &smc->cs[3].cycle);
  55
  56         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  57                 AT91_SMC_MODE_EXNW_DISABLE |
  58 #ifdef CONFIG_SYS_NAND_DBW_16
  59                 AT91_SMC_MODE_DBW_16 |
  60 #else /* CONFIG_SYS_NAND_DBW_8 */
  61                 AT91_SMC_MODE_DBW_8 |
  62 #endif
  63                 AT91_SMC_MODE_TDF_CYCLE(2),
  64                 &smc->cs[3].mode);
  65
  66         /* Configure RDY/BSY */
  67         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  68
  69         /* Enable NandFlash */
  70         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  71 }
  72 #endif
  73
  74 #ifdef CONFIG_MACB
  75 static void pm9263_macb_hw_init(void)
  76 {
  77         /*
  78          * PB27 enables the 50MHz oscillator for Ethernet PHY
  79          * 1 - enable
  80          * 0 - disable
  81          */
  82         at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
  83         at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
  84
  85         at91_periph_clk_enable(ATMEL_ID_EMAC);
  86
  87         /*
  88          * Disable pull-up on:
  89          *      RXDV (PC25) => PHY normal mode (not Test mode)
  90          *      ERX0 (PE25) => PHY ADDR0
  91          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  92          *
  93          * PHY has internal pull-down
  94          */
  95
  96         at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
  97         at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
  98         at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
  99
 100         /* Re-enable pull-up */
 101         at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
 102         at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
 103         at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
 104
 105         at91_macb_hw_init();
 106 }
 107 #endif
 108
 109 #ifdef CONFIG_LCD
 110
 111 #ifdef CONFIG_LCD_IN_PSRAM
 112
 113 #define PSRAM_CRE_PIN   AT91_PIO_PORTB, 29
 114 #define PSRAM_CTRL_REG  (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
 115
 116 /* Initialize the PSRAM memory */
 117 static int pm9263_lcd_hw_psram_init(void)
 118 {
 119         unsigned long csa;
 120         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
 121         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 122
 123         /* Enable CS3  3.3v, no pull-ups */
 124         csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
 125                 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
 126
 127         writel(csa, &matrix->csa[1]);
 128
 129         /* Configure SMC1 CS0 for PSRAM - 16-bit */
 130         writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
 131                 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
 132                 &smc->cs[0].setup);
 133
 134         writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
 135                 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
 136                 &smc->cs[0].pulse);
 137
 138         writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
 139                 &smc->cs[0].cycle);
 140
 141         writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
 142                 &smc->cs[0].mode);
 143
 144         /* setup PB29 as output */
 145         at91_set_pio_output(PSRAM_CRE_PIN, 1);
 146
 147         at91_set_pio_value(PSRAM_CRE_PIN, 0);   /* set PSRAM_CRE_PIN to '0' */
 148
 149         /* PSRAM: write BCR */
 150         readw(PSRAM_CTRL_REG);
 151         readw(PSRAM_CTRL_REG);
 152         writew(1, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 153         writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
 154
 155         /* write RCR of the PSRAM */
 156         readw(PSRAM_CTRL_REG);
 157         readw(PSRAM_CTRL_REG);
 158         writew(0, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 159         /* set RCR; 0x10-async mode,0x90-page mode */
 160         writew(0x90, PSRAM_CTRL_REG);
 161
 162         /*
 163          * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
 164          * MT45W2M16B - CRE must be 0
 165          * MT45W2M16A - CRE must be 1
 166          */
 167         writew(0x1234, PHYS_PSRAM);
 168         writew(0x5678, PHYS_PSRAM + 2);
 169
 170         /* test if the chip is MT45W2M16B */
 171         if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
 172                 /* try with CRE=1 (MT45W2M16A) */
 173                 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
 174
 175                 /* write RCR of the PSRAM */
 176                 readw(PSRAM_CTRL_REG);
 177                 readw(PSRAM_CTRL_REG);
 178                 writew(0, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 179                 /* set RCR;0x10-async mode,0x90-page mode */
 180                 writew(0x90, PSRAM_CTRL_REG);
 181
 182
 183                 writew(0x1234, PHYS_PSRAM);
 184                 writew(0x5678, PHYS_PSRAM+2);
 185                 if ((readw(PHYS_PSRAM) != 0x1234)
 186                   || (readw(PHYS_PSRAM + 2) != 0x5678))
 187                         return 1;
 188
 189         }
 190
 191         /* Bus matrix */
 192         writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
 193         writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
 194
 195         return 0;
 196 }
 197 #endif
 198
 199 static void pm9263_lcd_hw_init(void)
 200 {
 201         /* Power Control */
 202         at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
 203         at91_set_pio_value(AT91_PIO_PORTA, 22, 0);      /* power down */
 204
 205 #ifdef CONFIG_LCD_IN_PSRAM
 206         /* initialize te PSRAM */
 207         int stat = pm9263_lcd_hw_psram_init();
 208
 209         gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
 210 #else
 211         gd->fb_base = ATMEL_BASE_SRAM0;
 212 #endif
 213
 214 }
 215
 216 #endif /* CONFIG_LCD */
 217
 218 int board_early_init_f(void)
 219 {
 220         return 0;
 221 }
 222
 223 int board_init(void)
 224 {
 225         /* arch number of AT91SAM9263EK-Board */
 226         gd->bd->bi_arch_number = MACH_TYPE_PM9263;
 227
 228         /* adress of boot parameters */
 229         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 230
 231 #ifdef CONFIG_CMD_NAND
 232         pm9263_nand_hw_init();
 233 #endif
 234 #ifdef CONFIG_MACB
 235         pm9263_macb_hw_init();
 236 #endif
 237 #ifdef CONFIG_USB_OHCI_NEW
 238         at91_uhp_hw_init();
 239 #endif
 240 #ifdef CONFIG_LCD
 241         pm9263_lcd_hw_init();
 242 #endif
 243         return 0;
 244 }
 245
 246 int dram_init(void)
 247 {
 248         /* dram_init must store complete ramsize in gd->ram_size */
 249         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 250                                 PHYS_SDRAM_SIZE);
 251         return 0;
 252 }
 253
 254 int dram_init_banksize(void)
 255 {
 256         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 257         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 258
 259         return 0;
 260 }
 261
 262 #ifdef CONFIG_RESET_PHY_R
 263 void reset_phy(void)
 264 {
 265 }
 266 #endif
 267
 268 int board_eth_init(bd_t *bis)
 269 {
 270         int rc = 0;
 271 #ifdef CONFIG_MACB
 272         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
 273 #endif
 274         return rc;
 275 }
 276
 277 #ifdef CONFIG_DISPLAY_BOARDINFO
 278 int checkboard (void)
 279 {
 280         char *ss;
 281
 282         printf ("Board : Ronetix PM9263\n");
 283
 284         switch (gd->fb_base) {
 285         case PHYS_PSRAM:
 286                 ss = "(PSRAM)";
 287                 break;
 288
 289         case ATMEL_BASE_SRAM0:
 290                 ss = "(Internal SRAM)";
 291                 break;
 292
 293         default:
 294                 ss = "";
 295                 break;
 296         }
 297         printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
 298
 299         printf ("\n");
 300         return 0;
 301 }
 302 #endif