board/ronetix/pm9261/pm9261.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
   7  * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   8  */
   9
  10 #include <common.h>
  11 #include <init.h>
  12 #include <vsprintf.h>
  13 #include <asm/global_data.h>
  14 #include <linux/sizes.h>
  15 #include <asm/io.h>
  16 #include <asm/gpio.h>
  17 #include <asm/arch/at91sam9_smc.h>
  18 #include <asm/arch/at91_common.h>
  19 #include <asm/arch/at91_rstc.h>
  20 #include <asm/arch/at91_matrix.h>
  21 #include <asm/arch/clk.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/mach-types.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* ------------------------------------------------------------------------- */
  28 /*
  29  * Miscelaneous platform dependent initialisations
  30  */
  31
  32 #ifdef CONFIG_CMD_NAND
  33 static void pm9261_nand_hw_init(void)
  34 {
  35         unsigned long csa;
  36         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  37         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  38
  39         /* Enable CS3 */
  40         csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
  41         writel(csa, &matrix->csa);
  42
  43         /* Configure SMC CS3 for NAND/SmartMedia */
  44         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  45                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  46                 &smc->cs[3].setup);
  47
  48         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  49                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  50                 &smc->cs[3].pulse);
  51
  52         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  53                 &smc->cs[3].cycle);
  54
  55         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  56                 AT91_SMC_MODE_EXNW_DISABLE |
  57 #ifdef CONFIG_SYS_NAND_DBW_16
  58                 AT91_SMC_MODE_DBW_16 |
  59 #else /* CONFIG_SYS_NAND_DBW_8 */
  60                 AT91_SMC_MODE_DBW_8 |
  61 #endif
  62                 AT91_SMC_MODE_TDF_CYCLE(2),
  63                 &smc->cs[3].mode);
  64
  65         at91_periph_clk_enable(ATMEL_ID_PIOA);
  66         at91_periph_clk_enable(ATMEL_ID_PIOC);
  67
  68         /* Configure RDY/BSY */
  69         gpio_direction_input(CFG_SYS_NAND_READY_PIN);
  70
  71         /* Enable NandFlash */
  72         gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
  73
  74         at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* NANDOE */
  75         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* NANDWE */
  76 }
  77 #endif
  78
  79 int board_early_init_f(void)
  80 {
  81         return 0;
  82 }
  83
  84 int board_init(void)
  85 {
  86         /* arch number of PM9261-Board */
  87         gd->bd->bi_arch_number = MACH_TYPE_PM9261;
  88
  89         /* adress of boot parameters */
  90         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  91
  92 #ifdef CONFIG_CMD_NAND
  93         pm9261_nand_hw_init();
  94 #endif
  95 #ifdef CONFIG_DRIVER_DM9000
  96         pm9261_dm9000_hw_init();
  97 #endif
  98         return 0;
  99 }
 100
 101 int dram_init(void)
 102 {
 103         /* dram_init must store complete ramsize in gd->ram_size */
 104         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 105                                 PHYS_SDRAM_SIZE);
 106         return 0;
 107 }
 108
 109 int dram_init_banksize(void)
 110 {
 111         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 112         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 113
 114         return 0;
 115 }
 116
 117 #ifdef CONFIG_DISPLAY_BOARDINFO
 118 int checkboard (void)
 119 {
 120         char buf[32];
 121
 122         printf ("Board : Ronetix PM9261\n");
 123         printf ("Crystal frequency: %8s MHz\n",
 124                                         strmhz(buf, get_main_clk_rate()));
 125         printf ("CPU clock        : %8s MHz\n",
 126                                         strmhz(buf, get_cpu_clk_rate()));
 127         printf ("Master clock     : %8s MHz\n",
 128                                         strmhz(buf, get_mck_clk_rate()));
 129
 130         return 0;
 131 }
 132 #endif