1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/kernel.h>
8 #include <asm/arch/ddr.h>
9 #include <asm/arch/lpddr4_define.h>
11 #define WR_POST_EXT_3200 /* recommend to define */
13 struct dram_cfg_param lpddr4_ddrc_cfg[] = {
14 /* Start to config, default 3200mbps */
15 { DDRC_DBG1(0), 0x00000001 },
16 { DDRC_PWRCTL(0), 0x00000001 },
17 { DDRC_MSTR(0), 0xa1080020 },
18 { DDRC_MSTR2(0), 0x00000000 },
19 { DDRC_RFSHTMG(0), 0x006100E0 },
20 { DDRC_INIT0(0), 0xc003061c },
21 { DDRC_INIT1(0), 0x9e0000 },
22 { DDRC_INIT3(0), 0xd4002d },
23 #ifdef WR_POST_EXT_3200
24 { DDRC_INIT4(0), 0x00330008 },
26 { DDRC_INIT4(0), 0x00310008 },
28 { DDRC_INIT6(0), 0x0066004a },
29 { DDRC_INIT7(0), 0x0016004a },
31 { DDRC_DRAMTMG0(0), 0x1A201B22 },
32 { DDRC_DRAMTMG1(0), 0x00060633 },
33 { DDRC_DRAMTMG3(0), 0x00C0C000 },
34 { DDRC_DRAMTMG4(0), 0x0F04080F },
35 { DDRC_DRAMTMG5(0), 0x02040C0C },
36 { DDRC_DRAMTMG6(0), 0x01010007 },
37 { DDRC_DRAMTMG7(0), 0x00000401 },
38 { DDRC_DRAMTMG12(0), 0x00020600 },
39 { DDRC_DRAMTMG13(0), 0x0C100002 },
40 { DDRC_DRAMTMG14(0), 0x00000096 },
41 { DDRC_DRAMTMG17(0), 0x00A00050 },
43 { DDRC_ZQCTL0(0), 0xc3200018 },
44 { DDRC_ZQCTL1(0), 0x028061A8 },
45 { DDRC_ZQCTL2(0), 0x00000000 },
47 { DDRC_DFITMG0(0), 0x0497820A },
48 { DDRC_DFITMG1(0), 0x00080303 },
49 { DDRC_DFIUPD0(0), 0xE0400018 },
50 { DDRC_DFIUPD1(0), 0x00DF00E4 },
51 { DDRC_DFIUPD2(0), 0x80000000 },
52 { DDRC_DFIMISC(0), 0x00000011 },
53 { DDRC_DFITMG2(0), 0x0000170A },
55 { DDRC_DBICTL(0), 0x00000001 },
56 { DDRC_DFIPHYMSTR(0), 0x00000001 },
57 { DDRC_RANKCTL(0), 0x00000639 },
58 { DDRC_DRAMTMG2(0), 0x70e1617 },
61 { DDRC_ADDRMAP0(0), 0x0000001F },
62 { DDRC_ADDRMAP3(0), 0x00000000 },
63 { DDRC_ADDRMAP4(0), 0x00001F1F },
65 { DDRC_ADDRMAP1(0), 0x00080808 },
66 { DDRC_ADDRMAP5(0), 0x07070707 },
67 { DDRC_ADDRMAP6(0), 0xf070707 },
69 /* performance setting */
70 { DDRC_ODTCFG(0), 0x0b060908 },
71 { DDRC_ODTMAP(0), 0x00000000 },
72 { DDRC_SCHED(0), 0x29001505 },
73 { DDRC_SCHED1(0), 0x0000002c },
74 { DDRC_PERFHPR1(0), 0x5900575b },
75 /* 150T starve and 0x90 max tran len */
76 { DDRC_PERFLPR1(0), 0x90000096 },
77 /* 300T starve and 0x10 max tran len */
78 { DDRC_PERFWR1(0), 0x1000012c },
79 { DDRC_DBG0(0), 0x00000016 },
80 { DDRC_DBG1(0), 0x00000000 },
81 { DDRC_DBGCMD(0), 0x00000000 },
82 { DDRC_SWCTL(0), 0x00000001 },
83 { DDRC_POISONCFG(0), 0x00000011 },
84 { DDRC_PCCFG(0), 0x00000111 },
85 { DDRC_PCFGR_0(0), 0x000010f3 },
86 { DDRC_PCFGW_0(0), 0x000072ff },
87 { DDRC_PCTRL_0(0), 0x00000001 },
89 { DDRC_PCFGQOS0_0(0), 0x00000e00 },
90 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
91 /* disable Write Qos*/
92 { DDRC_PCFGWQOS0_0(0), 0x00000e00 },
93 { DDRC_PCFGWQOS1_0(0), 0x0000ffff },
95 /* Frequency 1: 400mbps */
96 { DDRC_FREQ1_DRAMTMG0(0), 0x0a040305 },
97 { DDRC_FREQ1_DRAMTMG1(0), 0x00030407 },
98 { DDRC_FREQ1_DRAMTMG2(0), 0x0203060b },
99 { DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
100 { DDRC_FREQ1_DRAMTMG4(0), 0x02040202 },
101 { DDRC_FREQ1_DRAMTMG5(0), 0x02030202 },
102 { DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
103 { DDRC_FREQ1_DRAMTMG7(0), 0x00000301 },
104 { DDRC_FREQ1_DRAMTMG14(0), 0x00000013 },
105 { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
106 { DDRC_FREQ1_DRAMTMG17(0), 0x0014000a },
107 { DDRC_FREQ1_DERATEINT(0), 0x00007d00 },
108 { DDRC_FREQ1_DFITMG0(0), 0x3818200 },
109 { DDRC_FREQ1_DFITMG2(0), 0x00000100 },
110 { DDRC_FREQ1_RFSHTMG(0), 0xc0012 },
111 { DDRC_FREQ1_INIT3(0), 0x840000 },
112 { DDRC_FREQ1_INIT4(0), 0x310000 },
113 { DDRC_FREQ1_INIT6(0), 0x66004a },
114 { DDRC_FREQ1_INIT7(0), 0x16004a },
116 /* Frequency 2: 100mbps */
117 { DDRC_FREQ2_DRAMTMG0(0), 0xa010102 },
118 { DDRC_FREQ2_DRAMTMG1(0), 0x30404 },
119 { DDRC_FREQ2_DRAMTMG2(0), 0x203060b },
120 { DDRC_FREQ2_DRAMTMG3(0), 0x505000 },
121 { DDRC_FREQ2_DRAMTMG4(0), 0x2040202 },
122 { DDRC_FREQ2_DRAMTMG5(0), 0x2030202 },
123 { DDRC_FREQ2_DRAMTMG6(0), 0x1010004 },
124 { DDRC_FREQ2_DRAMTMG7(0), 0x301 },
125 { DDRC_FREQ2_DRAMTMG14(0), 0x5 },
126 { DDRC_FREQ2_DRAMTMG17(0), 0x50003 },
127 { DDRC_FREQ2_DERATEINT(0), 0x1f40 },
128 { DDRC_FREQ2_DFITMG0(0), 0x3818200 },
129 { DDRC_FREQ2_DFITMG2(0), 0x00000100 },
130 { DDRC_FREQ2_RFSHTMG(0), 0x30005 },
131 { DDRC_FREQ2_INIT3(0), 0x840000 },
132 { DDRC_FREQ2_INIT4(0), 0x310000 },
133 { DDRC_FREQ2_INIT6(0), 0x66004a },
134 { DDRC_FREQ2_INIT7(0), 0x16004a },
137 /* PHY Initialize Configuration */
138 struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
271 { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
272 { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
273 { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
274 { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
275 { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
276 { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
277 { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
278 { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
279 { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
280 { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
347 /* ddr phy trained csr */
348 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1070 /* P0 message block parameter for training firmware */
1071 struct dram_cfg_param lpddr4_fsp0_cfg[] = {
1075 { 0x54005, 0x2228 },
1077 { 0x54008, 0x131f },
1081 { 0x54019, 0x2dd4 },
1083 { 0x5401b, 0x4a66 },
1084 { 0x5401c, 0x4a08 },
1086 { 0x5401f, 0x2dd4 },
1088 { 0x54021, 0x4a66 },
1089 { 0x54022, 0x4a08 },
1091 { 0x5402b, 0x1000 },
1093 { 0x54032, 0xd400 },
1094 { 0x54033, 0x312d },
1095 { 0x54034, 0x6600 },
1098 { 0x54037, 0x1600 },
1099 { 0x54038, 0xd400 },
1100 { 0x54039, 0x312d },
1101 { 0x5403a, 0x6600 },
1104 { 0x5403d, 0x1600 },
1108 /* P1 message block parameter for training firmware */
1109 struct dram_cfg_param lpddr4_fsp1_cfg[] = {
1114 { 0x54005, 0x2228 },
1116 { 0x54008, 0x121f },
1122 { 0x5401b, 0x4a66 },
1123 { 0x5401c, 0x4a08 },
1127 { 0x54021, 0x4a66 },
1128 { 0x54022, 0x4a08 },
1130 { 0x5402b, 0x1000 },
1132 { 0x54032, 0x8400 },
1133 { 0x54033, 0x3100 },
1134 { 0x54034, 0x6600 },
1137 { 0x54037, 0x1600 },
1138 { 0x54038, 0x8400 },
1139 { 0x54039, 0x3100 },
1140 { 0x5403a, 0x6600 },
1143 { 0x5403d, 0x1600 },
1147 /* P2 message block parameter for training firmware */
1148 struct dram_cfg_param lpddr4_fsp2_cfg[] = {
1153 { 0x54005, 0x2228 },
1155 { 0x54008, 0x121f },
1161 { 0x5401b, 0x4a66 },
1162 { 0x5401c, 0x4a08 },
1166 { 0x54021, 0x4a66 },
1167 { 0x54022, 0x4a08 },
1169 { 0x5402b, 0x1000 },
1171 { 0x54032, 0x8400 },
1172 { 0x54033, 0x3100 },
1173 { 0x54034, 0x6600 },
1176 { 0x54037, 0x1600 },
1177 { 0x54038, 0x8400 },
1178 { 0x54039, 0x3100 },
1179 { 0x5403a, 0x6600 },
1182 { 0x5403d, 0x1600 },
1186 /* P0 2D message block parameter for training firmware */
1187 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
1191 { 0x54005, 0x2228 },
1197 { 0x54010, 0x1f7f },
1199 { 0x54019, 0x2dd4 },
1201 { 0x5401b, 0x4a66 },
1202 { 0x5401c, 0x4a08 },
1204 { 0x5401f, 0x2dd4 },
1206 { 0x54021, 0x4a66 },
1207 { 0x54022, 0x4a08 },
1209 { 0x5402b, 0x1000 },
1211 { 0x54032, 0xd400 },
1212 { 0x54033, 0x312d },
1213 { 0x54034, 0x6600 },
1216 { 0x54037, 0x1600 },
1217 { 0x54038, 0xd400 },
1218 { 0x54039, 0x312d },
1219 { 0x5403a, 0x6600 },
1222 { 0x5403d, 0x1600 },
1226 /* DRAM PHY init engine image */
1227 struct dram_cfg_param lpddr4_phy_pie[] = {
1286 { 0x9005c, 0x40c0 },
1292 { 0x90062, 0x4040 },
1365 { 0x40001, 0x4008 },
1369 { 0x40002, 0x4040 },
1379 { 0x40044, 0x1740 },
1387 { 0x40046, 0x2001 },
1391 { 0x40047, 0x2800 },
1399 { 0x40049, 0x1400 },
1409 { 0x4000c, 0x4028 },
1421 { 0x4000f, 0x4040 },
1425 { 0x40010, 0x2604 },
1432 { 0x40071, 0x2002 },
1437 { 0x40013, 0x2604 },
1444 { 0x40074, 0x2002 },
1445 { 0x40015, 0x4040 },
1451 { 0x40056, 0x1200 },
1455 { 0x40057, 0x1300 },
1459 { 0x40058, 0x1200 },
1463 { 0x40059, 0x1300 },
1465 { 0x4001a, 0x4808 },
1503 { 0x900c9, 0x8568 },
1512 { 0x900d2, 0x8558 },
1517 { 0x900d7, 0x1ff8 },
1518 { 0x900d8, 0x85a8 },
1527 { 0x900e1, 0x8310 },
1530 { 0x900e4, 0xa310 },
1542 { 0x900f0, 0x8310 },
1545 { 0x900f3, 0xa310 },
1547 { 0x900f5, 0x1ff8 },
1548 { 0x900f6, 0x85a8 },
1560 { 0x90102, 0x8b10 },
1563 { 0x90105, 0xab10 },
1575 { 0x90111, 0x8b10 },
1578 { 0x90114, 0xab10 },
1593 { 0x90123, 0x8080 },
1608 { 0x90132, 0x8080 },
1614 { 0x90138, 0x8568 },
1623 { 0x90141, 0x8558 },
1635 { 0x9014d, 0x8558 },
1653 { 0x9015f, 0x8140 },
1656 { 0x90162, 0x8138 },
1686 { 0x90180, 0x8140 },
1731 { 0x9000f, 0x6110 },
1732 { 0x90010, 0x2152 },
1733 { 0x90011, 0xdfbd },
1735 { 0x90013, 0x6152 },
1765 { 0x10002, 0x6209 },
1779 { 0x11002, 0x6209 },
1793 { 0x12002, 0x6209 },
1807 { 0x13002, 0x6209 },
1822 struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
1826 .fw_type = FW_1D_IMAGE,
1827 .fsp_cfg = lpddr4_fsp0_cfg,
1828 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
1833 .fw_type = FW_1D_IMAGE,
1834 .fsp_cfg = lpddr4_fsp1_cfg,
1835 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
1840 .fw_type = FW_1D_IMAGE,
1841 .fsp_cfg = lpddr4_fsp2_cfg,
1842 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
1847 .fw_type = FW_2D_IMAGE,
1848 .fsp_cfg = lpddr4_fsp0_2d_cfg,
1849 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
1853 /* lpddr4 timing config params on EVK board */
1854 struct dram_timing_info dram_timing = {
1855 .ddrc_cfg = lpddr4_ddrc_cfg,
1856 .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1857 .ddrphy_cfg = lpddr4_ddrphy_cfg,
1858 .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1859 .fsp_msg = lpddr4_dram_fsp_msg,
1860 .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1861 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1862 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1863 .ddrphy_pie = lpddr4_phy_pie,
1864 .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
1865 .fsp_table = { 3200, 400, 100, },