1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm-generic/gpio.h>
9 #include <asm/arch/imx8mq_pins.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/clock.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
17 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
19 static iomux_v3_cfg_t const wdog_pads[] = {
20 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
23 static iomux_v3_cfg_t const uart_pads[] = {
24 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
25 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
28 int board_early_init_f(void)
30 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
32 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
35 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
40 static int setup_fec(void)
42 struct iomuxc_gpr_base_regs *gpr =
43 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
45 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
46 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
47 return set_clk_enet(ENET_125MHZ);
50 int board_phy_config(struct phy_device *phydev)
52 /* enable rgmii rxc skew and phy mode select to RGMII copper */
53 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
54 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
56 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
57 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
59 if (phydev->drv->config)
60 phydev->drv->config(phydev);
71 int board_mmc_get_env_dev(int devno)
76 int board_late_init(void)
78 if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
79 env_set("board_name", "imx8mq-cm");
80 env_set("board_rev", "v2.0");