board/rockchip/evb_px5/evb-px5.c

   1 /*
   2  * Copyright (c) 2017 Andy Yan
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <fdtdec.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/grf_rk3368.h>
  11
  12 DECLARE_GLOBAL_DATA_PTR;
  13
  14 int mach_cpu_init(void)
  15 {
  16         struct rk3368_pmu_grf *pmugrf;
  17         int node;
  18
  19         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rk3368-pmugrf");
  20         pmugrf = (struct rk3368_pmu_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
  21
  22         rk_clrsetreg(&pmugrf->gpio0d_iomux,
  23                      GPIO0D0_MASK | GPIO0D1_MASK |
  24                      GPIO0D2_MASK | GPIO0D3_MASK,
  25                      GPIO0D0_GPIO << GPIO0D0_SHIFT |
  26                      GPIO0D1_GPIO << GPIO0D1_SHIFT |
  27                      GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
  28                      GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
  29         return 0;
  30 }
  31
  32 int board_init(void)
  33 {
  34         return 0;
  35 }
  36
  37 int dram_init(void)
  38 {
  39         gd->ram_size = 0x40000000;
  40
  41         return 0;
  42 }
  43
  44 int dram_init_banksize(void)
  45 {
  46          /* Reserve 0x200000 for ATF bl31 */
  47         gd->bd->bi_dram[0].start = 0x200000;
  48         gd->bd->bi_dram[0].size = 0x3fe00000;
  49
  50         return 0;
  51 }