board/renesas/v3hsk/cpld.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * V3HSK board CPLD access support
   4  *
   5  * Copyright (C) 2019 Renesas Electronics Corporation
   6  * Copyright (C) 2019 Cogent Embedded, Inc.
   7  *
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <i2c.h>
  14 #include <linux/err.h>
  15 #include <sysreset.h>
  16 #include <command.h>
  17
  18 #define CPLD_ADDR_PRODUCT_0             0x0000 /* R */
  19 #define CPLD_ADDR_PRODUCT_1             0x0001 /* R */
  20 #define CPLD_ADDR_PRODUCT_2             0x0002 /* R */
  21 #define CPLD_ADDR_PRODUCT_3             0x0003 /* R */
  22 #define CPLD_ADDR_CPLD_VERSION_D        0x0004 /* R */
  23 #define CPLD_ADDR_CPLD_VERSION_M        0x0005 /* R */
  24 #define CPLD_ADDR_CPLD_VERSION_Y_0      0x0006 /* R */
  25 #define CPLD_ADDR_CPLD_VERSION_Y_1      0x0007 /* R */
  26 #define CPLD_ADDR_MODE_SET_0            0x0008 /* R */
  27 #define CPLD_ADDR_MODE_SET_1            0x0009 /* R */
  28 #define CPLD_ADDR_MODE_SET_2            0x000A /* R */
  29 #define CPLD_ADDR_MODE_SET_3            0x000B /* R */
  30 #define CPLD_ADDR_MODE_SET_4            0x000C /* R */
  31 #define CPLD_ADDR_MODE_LAST_0           0x0018 /* R */
  32 #define CPLD_ADDR_MODE_LAST_1           0x0019 /* R */
  33 #define CPLD_ADDR_MODE_LAST_2           0x001A /* R */
  34 #define CPLD_ADDR_MODE_LAST_3           0x001B /* R */
  35 #define CPLD_ADDR_MODE_LAST_4           0x001C /* R */
  36 #define CPLD_ADDR_DIPSW4                0x0020 /* R */
  37 #define CPLD_ADDR_DIPSW5                0x0021 /* R */
  38 #define CPLD_ADDR_RESET                 0x0024 /* R/W */
  39 #define CPLD_ADDR_POWER_CFG             0x0025 /* R/W */
  40 #define CPLD_ADDR_PERI_CFG_0            0x0030 /* R/W */
  41 #define CPLD_ADDR_PERI_CFG_1            0x0031 /* R/W */
  42 #define CPLD_ADDR_PERI_CFG_2            0x0032 /* R/W */
  43 #define CPLD_ADDR_PERI_CFG_3            0x0033 /* R/W */
  44 #define CPLD_ADDR_LEDS                  0x0034 /* R/W */
  45 #define CPLD_ADDR_LEDS_CFG              0x0035 /* R/W */
  46 #define CPLD_ADDR_UART_CFG              0x0036 /* R/W */
  47 #define CPLD_ADDR_UART_STATUS           0x0037 /* R */
  48
  49 #define CPLD_ADDR_PCB_VERSION_0         0x1000 /* R */
  50 #define CPLD_ADDR_PCB_VERSION_1         0x1001 /* R */
  51 #define CPLD_ADDR_SOC_VERSION_0         0x1002 /* R */
  52 #define CPLD_ADDR_SOC_VERSION_1         0x1003 /* R */
  53 #define CPLD_ADDR_PCB_SN_0              0x1004 /* R */
  54 #define CPLD_ADDR_PCB_SN_1              0x1005 /* R */
  55
  56 static u16 cpld_read(struct udevice *dev, u16 addr)
  57 {
  58         u8 data[2];
  59
  60         /* Random flash reads require 2 reads: first read is unreliable */
  61         if (addr >= CPLD_ADDR_PCB_VERSION_0)
  62                 dm_i2c_read(dev, addr, data, 2);
  63
  64         /* Only the second byte read is valid */
  65         dm_i2c_read(dev, addr, data, 2);
  66         return data[1];
  67 }
  68
  69 static void cpld_write(struct udevice *dev, u16 addr, u8 data)
  70 {
  71         dm_i2c_write(dev, addr, &data, 1);
  72 }
  73
  74 static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
  75 {
  76         struct udevice *dev;
  77         u16 addr, val;
  78         int ret;
  79
  80         ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
  81                                           DM_DRIVER_GET(sysreset_renesas_v3hsk),
  82                                           &dev);
  83         if (ret)
  84                 return ret;
  85
  86         if (argc == 2 && strcmp(argv[1], "info") == 0) {
  87                 printf("Product:                0x%08x\n",
  88                        (cpld_read(dev, CPLD_ADDR_PRODUCT_3) << 24) |
  89                        (cpld_read(dev, CPLD_ADDR_PRODUCT_2) << 16) |
  90                        (cpld_read(dev, CPLD_ADDR_PRODUCT_1) << 8) |
  91                        cpld_read(dev, CPLD_ADDR_PRODUCT_0));
  92                 printf("CPLD version:           0x%08x\n",
  93                        (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_1) << 24) |
  94                        (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_0) << 16) |
  95                        (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_M) << 8) |
  96                        cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
  97                 printf("Mode setting (MD0..26): 0x%08x\n",
  98                        (cpld_read(dev, CPLD_ADDR_MODE_LAST_3) << 24) |
  99                        (cpld_read(dev, CPLD_ADDR_MODE_LAST_2) << 16) |
 100                        (cpld_read(dev, CPLD_ADDR_MODE_LAST_1) << 8) |
 101                        cpld_read(dev, CPLD_ADDR_MODE_LAST_0));
 102                 printf("DIPSW (SW4, SW5):       0x%02x, 0x%x\n",
 103                        cpld_read(dev, CPLD_ADDR_DIPSW4) ^ 0xff,
 104                        (cpld_read(dev, CPLD_ADDR_DIPSW5) ^ 0xff) & 0xf);
 105                 printf("Power config:           0x%08x\n",
 106                        cpld_read(dev, CPLD_ADDR_POWER_CFG));
 107                 printf("Periferals config:      0x%08x\n",
 108                        (cpld_read(dev, CPLD_ADDR_PERI_CFG_3) << 24) |
 109                        (cpld_read(dev, CPLD_ADDR_PERI_CFG_2) << 16) |
 110                        (cpld_read(dev, CPLD_ADDR_PERI_CFG_1) << 8) |
 111                        cpld_read(dev, CPLD_ADDR_PERI_CFG_0));
 112                 printf("PCB version:            %d.%d\n",
 113                        cpld_read(dev, CPLD_ADDR_PCB_VERSION_1),
 114                        cpld_read(dev, CPLD_ADDR_PCB_VERSION_0));
 115                 printf("SOC version:            %d.%d\n",
 116                        cpld_read(dev, CPLD_ADDR_SOC_VERSION_1),
 117                        cpld_read(dev, CPLD_ADDR_SOC_VERSION_0));
 118                 printf("PCB S/N:                %d\n",
 119                        (cpld_read(dev, CPLD_ADDR_PCB_SN_1) << 8) |
 120                        cpld_read(dev, CPLD_ADDR_PCB_SN_0));
 121                 return 0;
 122         }
 123
 124         if (argc < 3)
 125                 return CMD_RET_USAGE;
 126
 127         addr = simple_strtoul(argv[2], NULL, 16);
 128         if (!(addr >= CPLD_ADDR_PRODUCT_0 && addr <= CPLD_ADDR_UART_STATUS)) {
 129                 printf("cpld invalid addr\n");
 130                 return CMD_RET_USAGE;
 131         }
 132
 133         if (argc == 3 && strcmp(argv[1], "read") == 0) {
 134                 printf("0x%x\n", cpld_read(dev, addr));
 135         } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
 136                 val = simple_strtoul(argv[3], NULL, 16);
 137                 cpld_write(dev, addr, val);
 138         }
 139
 140         return 0;
 141 }
 142
 143 U_BOOT_CMD(cpld, 4, 1, do_cpld,
 144            "CPLD access",
 145            "info\n"
 146            "cpld read addr\n"
 147            "cpld write addr val\n"
 148 );
 149
 150 static int renesas_v3hsk_sysreset_request(struct udevice *dev, enum sysreset_t type)
 151 {
 152         cpld_write(dev, CPLD_ADDR_RESET, 1);
 153
 154         return -EINPROGRESS;
 155 }
 156
 157 static int renesas_v3hsk_sysreset_probe(struct udevice *dev)
 158 {
 159         if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
 160                 return -EPROTONOSUPPORT;
 161
 162         return 0;
 163 }
 164
 165 static struct sysreset_ops renesas_v3hsk_sysreset = {
 166         .request        = renesas_v3hsk_sysreset_request,
 167 };
 168
 169 static const struct udevice_id renesas_v3hsk_sysreset_ids[] = {
 170         { .compatible = "renesas,v3hsk-cpld" },
 171         { /* sentinel */ }
 172 };
 173
 174 U_BOOT_DRIVER(sysreset_renesas_v3hsk) = {
 175         .name           = "renesas_v3hsk_sysreset",
 176         .id             = UCLASS_SYSRESET,
 177         .ops            = &renesas_v3hsk_sysreset,
 178         .probe          = renesas_v3hsk_sysreset_probe,
 179         .of_match       = renesas_v3hsk_sysreset_ids,
 180 };