1 // SPDX-License-Identifier: GPL-2.0+
3 * board/renesas/ulcb/ulcb.c
4 * This file is ULCB board support.
6 * Copyright (C) 2017 Renesas Electronics Corporation
15 #include <dm/platform_data/serial_sh.h>
16 #include <asm/processor.h>
17 #include <asm/mach-types.h>
19 #include <linux/bitops.h>
20 #include <linux/errno.h>
21 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/rmobile.h>
25 #include <asm/arch/rcar-mstp.h>
26 #include <asm/arch/sh_sdhi.h>
30 DECLARE_GLOBAL_DATA_PTR;
36 #define DVFS_MSTP926 BIT(26)
37 #define HSUSB_MSTP704 BIT(4) /* HSUSB */
39 int board_early_init_f(void)
41 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
43 mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
48 /* HSUSB block registers */
49 #define HSUSB_REG_LPSTS 0xE6590102
50 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
51 #define HSUSB_REG_UGCTRL2 0xE6590184
52 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
53 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
57 /* adress of boot parameters */
58 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
61 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
63 /* Configure the HSUSB block */
64 mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
66 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
67 HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
68 /* low power status */
69 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
74 #ifdef CONFIG_MULTI_DTB_FIT
75 int board_fit_config_name_match(const char *name)
77 /* PRR driver is not available yet */
78 u32 cpu_type = rmobile_get_cpu_type();
80 if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
81 !strcmp(name, "r8a77950-ulcb-u-boot"))
84 if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
85 !strcmp(name, "r8a77960-ulcb-u-boot"))
88 if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
89 !strcmp(name, "r8a77965-ulcb-u-boot"))