1 // SPDX-License-Identifier: GPL-2.0+
3 * board/renesas/ulcb/ulcb.c
4 * This file is ULCB board support.
6 * Copyright (C) 2017 Renesas Electronics Corporation
15 #include <dm/platform_data/serial_sh.h>
16 #include <asm/processor.h>
17 #include <asm/mach-types.h>
19 #include <linux/errno.h>
20 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/rmobile.h>
24 #include <asm/arch/rcar-mstp.h>
25 #include <asm/arch/sh_sdhi.h>
29 DECLARE_GLOBAL_DATA_PTR;
35 #define DVFS_MSTP926 BIT(26)
36 #define HSUSB_MSTP704 BIT(4) /* HSUSB */
38 int board_early_init_f(void)
40 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
42 mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
47 /* HSUSB block registers */
48 #define HSUSB_REG_LPSTS 0xE6590102
49 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
50 #define HSUSB_REG_UGCTRL2 0xE6590184
51 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
52 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
56 /* adress of boot parameters */
57 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
60 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
62 /* Configure the HSUSB block */
63 mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
65 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
66 HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
67 /* low power status */
68 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
73 #ifdef CONFIG_MULTI_DTB_FIT
74 int board_fit_config_name_match(const char *name)
76 /* PRR driver is not available yet */
77 u32 cpu_type = rmobile_get_cpu_type();
79 if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
80 !strcmp(name, "r8a77950-ulcb-u-boot"))
83 if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
84 !strcmp(name, "r8a77960-ulcb-u-boot"))
87 if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
88 !strcmp(name, "r8a77965-ulcb-u-boot"))