1 // SPDX-License-Identifier: GPL-2.0+
3 * board/renesas/ulcb/ulcb.c
4 * This file is ULCB board support.
6 * Copyright (C) 2017 Renesas Electronics Corporation
15 #include <asm/global_data.h>
16 #include <dm/platform_data/serial_sh.h>
17 #include <asm/processor.h>
18 #include <asm/mach-types.h>
20 #include <linux/bitops.h>
21 #include <linux/errno.h>
22 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/rmobile.h>
26 #include <asm/arch/rcar-mstp.h>
27 #include <asm/arch/sh_sdhi.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define DVFS_MSTP926 BIT(26)
34 #define HSUSB_MSTP704 BIT(4) /* HSUSB */
36 int board_early_init_f(void)
38 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
40 mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
45 /* HSUSB block registers */
46 #define HSUSB_REG_LPSTS 0xE6590102
47 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
48 #define HSUSB_REG_UGCTRL2 0xE6590184
49 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
50 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
54 /* adress of boot parameters */
55 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
58 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
60 /* Configure the HSUSB block */
61 mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
63 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
64 HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
65 /* low power status */
66 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
71 #ifdef CONFIG_MULTI_DTB_FIT
72 int board_fit_config_name_match(const char *name)
74 /* PRR driver is not available yet */
75 u32 cpu_type = rmobile_get_cpu_type();
77 if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
78 !strcmp(name, "r8a77950-ulcb-u-boot"))
81 if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
82 !strcmp(name, "r8a77960-ulcb-u-boot"))
85 if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
86 !strcmp(name, "r8a77965-ulcb-u-boot"))