2 * board/renesas/salvator-x/salvator-x.c
3 * This file is Salvator-X board support.
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
6 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <dm/platform_data/serial_sh.h>
16 #include <asm/processor.h>
17 #include <asm/mach-types.h>
19 #include <linux/errno.h>
20 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/rmobile.h>
24 #include <asm/arch/rcar-mstp.h>
25 #include <asm/arch/sh_sdhi.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define CPGWPCR 0xE6150904
32 #define CPGWPR 0xE615090C
34 #define CLK2MHZ(clk) (clk / 1000 / 1000)
37 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
38 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
41 writel(0xA5A5A500, &rwdt->rwtcsra);
42 writel(0xA5A5A500, &swdt->swtcsra);
44 writel(0xA5A50000, CPGWPCR);
45 writel(0xFFFFFFFF, CPGWPR);
48 #define GSX_MSTP112 BIT(12) /* 3DG */
49 #define TMU0_MSTP125 BIT(25) /* secure */
50 #define TMU1_MSTP124 BIT(24) /* non-secure */
51 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */
52 #define SD0_MSTP314 BIT(14)
53 #define SD1_MSTP313 BIT(13)
54 #define SD2_MSTP312 BIT(12) /* either MMC0 */
55 #define SD3_MSTP311 BIT(11) /* either MMC1 */
57 #define SD0CKCR 0xE6150074
58 #define SD1CKCR 0xE6150078
59 #define SD2CKCR 0xE6150268
60 #define SD3CKCR 0xE615026C
62 int board_early_init_f(void)
64 /* TMU0,1 */ /* which use ? */
65 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
67 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
69 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
71 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
82 /* R/- 32 Power status register 2(3DG) */
83 #define SYSC_PWRSR2 0xE6180100
84 /* -/W 32 Power resume control register 2 (3DG) */
85 #define SYSC_PWRONCR2 0xE618010C
89 /* adress of boot parameters */
90 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
92 /* Init PFC controller */
93 r8a7795_pinmux_init();
95 /* GSX: force power and clock supply */
96 writel(0x0000001F, SYSC_PWRONCR2);
97 while (readl(SYSC_PWRSR2) != 0x000003E0)
100 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
105 #ifdef CONFIG_SH_SDHI
106 int board_mmc_init(bd_t *bis)
111 gpio_request(GPIO_GFN_SD0_DAT0, NULL);
112 gpio_request(GPIO_GFN_SD0_DAT1, NULL);
113 gpio_request(GPIO_GFN_SD0_DAT2, NULL);
114 gpio_request(GPIO_GFN_SD0_DAT3, NULL);
115 gpio_request(GPIO_GFN_SD0_CLK, NULL);
116 gpio_request(GPIO_GFN_SD0_CMD, NULL);
117 gpio_request(GPIO_GFN_SD0_CD, NULL);
118 gpio_request(GPIO_GFN_SD0_WP, NULL);
120 gpio_request(GPIO_GP_5_2, NULL);
121 gpio_request(GPIO_GP_5_1, NULL);
122 gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
123 gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
125 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
126 SH_SDHI_QUIRK_64BIT_BUF);
130 /* SDHI1/SDHI2 eMMC */
131 gpio_request(GPIO_GFN_SD1_DAT0, NULL);
132 gpio_request(GPIO_GFN_SD1_DAT1, NULL);
133 gpio_request(GPIO_GFN_SD1_DAT2, NULL);
134 gpio_request(GPIO_GFN_SD1_DAT3, NULL);
135 gpio_request(GPIO_GFN_SD2_DAT0, NULL);
136 gpio_request(GPIO_GFN_SD2_DAT1, NULL);
137 gpio_request(GPIO_GFN_SD2_DAT2, NULL);
138 gpio_request(GPIO_GFN_SD2_DAT3, NULL);
139 gpio_request(GPIO_GFN_SD2_CLK, NULL);
140 gpio_request(GPIO_GFN_SD2_CMD, NULL);
141 gpio_request(GPIO_GP_5_3, NULL);
142 gpio_request(GPIO_GP_5_9, NULL);
143 gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
144 gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
146 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
147 SH_SDHI_QUIRK_64BIT_BUF);
152 gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
153 gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
154 gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
155 gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
156 gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
157 gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
159 gpio_request(GPIO_FN_SD3_CD, NULL);
160 gpio_request(GPIO_FN_SD3_WP, NULL);
162 gpio_request(GPIO_GP_3_15, NULL);
163 gpio_request(GPIO_GP_3_14, NULL);
164 gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
165 gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
167 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
168 SH_SDHI_QUIRK_64BIT_BUF);
175 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
180 const struct rmobile_sysinfo sysinfo = {
181 CONFIG_RCAR_BOARD_STRING
184 #define RST_BASE 0xE6160000
185 #define RST_CA57RESCNT (RST_BASE + 0x40)
186 #define RST_CA53RESCNT (RST_BASE + 0x44)
187 #define RST_RSTOUTCR (RST_BASE + 0x58)
188 #define RST_CODE 0xA5A5000F
190 void reset_cpu(ulong addr)
193 writel(RST_CODE, RST_CA57RESCNT);
196 static const struct sh_serial_platdata serial_platdata = {
199 .clk = CONFIG_SH_SCIF_CLK_FREQ,
203 U_BOOT_DEVICE(salvator_x_scif2) = {
205 .platdata = &serial_platdata,