2 * board/renesas/salvator-x/salvator-x.c
3 * This file is Salvator-X/Salvator-XS board support.
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
6 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <dm/platform_data/serial_sh.h>
16 #include <asm/processor.h>
17 #include <asm/mach-types.h>
19 #include <linux/errno.h>
20 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/rmobile.h>
24 #include <asm/arch/rcar-mstp.h>
25 #include <asm/arch/sh_sdhi.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define CPGWPCR 0xE6150904
32 #define CPGWPR 0xE615090C
34 #define CLK2MHZ(clk) (clk / 1000 / 1000)
37 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
38 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
41 writel(0xA5A5A500, &rwdt->rwtcsra);
42 writel(0xA5A5A500, &swdt->swtcsra);
44 writel(0xA5A50000, CPGWPCR);
45 writel(0xFFFFFFFF, CPGWPR);
48 #define GSX_MSTP112 BIT(12) /* 3DG */
49 #define TMU0_MSTP125 BIT(25) /* secure */
50 #define TMU1_MSTP124 BIT(24) /* non-secure */
51 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */
52 #define DVFS_MSTP926 BIT(26)
53 #define HSUSB_MSTP704 BIT(4) /* HSUSB */
55 int board_early_init_f(void)
57 /* TMU0,1 */ /* which use ? */
58 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
60 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
62 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
68 /* R/- 32 Power status register 2(3DG) */
69 #define SYSC_PWRSR2 0xE6180100
70 /* -/W 32 Power resume control register 2 (3DG) */
71 #define SYSC_PWRONCR2 0xE618010C
73 /* HSUSB block registers */
74 #define HSUSB_REG_LPSTS 0xE6590102
75 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
76 #define HSUSB_REG_UGCTRL2 0xE6590184
77 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
78 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
82 /* adress of boot parameters */
83 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
85 #if defined(CONFIG_R8A7795)
86 /* GSX: force power and clock supply */
87 writel(0x0000001F, SYSC_PWRONCR2);
88 while (readl(SYSC_PWRSR2) != 0x000003E0)
91 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
95 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
97 /* Configure the HSUSB block */
98 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
100 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
101 HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
102 /* low power status */
103 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
110 gd->ram_size = PHYS_SDRAM_1_SIZE;
111 #if (CONFIG_NR_DRAM_BANKS >= 2)
112 gd->ram_size += PHYS_SDRAM_2_SIZE;
114 #if (CONFIG_NR_DRAM_BANKS >= 3)
115 gd->ram_size += PHYS_SDRAM_3_SIZE;
117 #if (CONFIG_NR_DRAM_BANKS >= 4)
118 gd->ram_size += PHYS_SDRAM_4_SIZE;
124 int dram_init_banksize(void)
126 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
127 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
128 #if (CONFIG_NR_DRAM_BANKS >= 2)
129 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
130 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
132 #if (CONFIG_NR_DRAM_BANKS >= 3)
133 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
134 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
136 #if (CONFIG_NR_DRAM_BANKS >= 4)
137 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
138 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
143 const struct rmobile_sysinfo sysinfo = {
144 CONFIG_RCAR_BOARD_STRING
147 #define RST_BASE 0xE6160000
148 #define RST_CA57RESCNT (RST_BASE + 0x40)
149 #define RST_CA53RESCNT (RST_BASE + 0x44)
150 #define RST_RSTOUTCR (RST_BASE + 0x58)
151 #define RST_CODE 0xA5A5000F
153 void reset_cpu(ulong addr)
155 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
156 i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
159 writel(RST_CODE, RST_CA57RESCNT);