board/renesas/porter/porter_spl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * board/renesas/porter/porter_spl.c
   4  *
   5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <init.h>
  11 #include <malloc.h>
  12 #include <dm/platform_data/serial_sh.h>
  13 #include <asm/processor.h>
  14 #include <asm/mach-types.h>
  15 #include <asm/io.h>
  16 #include <linux/bitops.h>
  17 #include <linux/errno.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/gpio.h>
  20 #include <asm/arch/rmobile.h>
  21 #include <asm/arch/rcar-mstp.h>
  22
  23 #include <spl.h>
  24
  25 #define TMU0_MSTP125    BIT(25)
  26 #define SCIF0_MSTP721   BIT(21)
  27 #define QSPI_MSTP917    BIT(17)
  28
  29 #define SD2CKCR         0xE615026C
  30 #define SD_97500KHZ     0x7
  31
  32 struct reg_config {
  33         u16     off;
  34         u32     val;
  35 };
  36
  37 static void dbsc_wait(u16 reg)
  38 {
  39         static const u32 dbsc3_0_base = DBSC3_0_BASE;
  40         static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
  41
  42         while (!(readl(dbsc3_0_base + reg) & BIT(0)))
  43                 ;
  44
  45         while (!(readl(dbsc3_1_base + reg) & BIT(0)))
  46                 ;
  47 }
  48
  49 static void spl_init_sys(void)
  50 {
  51         u32 r0 = 0;
  52
  53         writel(0xa5a5a500, 0xe6020004);
  54         writel(0xa5a5a500, 0xe6030004);
  55
  56         asm volatile(
  57                 /* ICIALLU - Invalidate I$ to PoU */
  58                 "mcr    15, 0, %0, cr7, cr5, 0  \n"
  59                 /* BPIALL - Invalidate branch predictors */
  60                 "mcr    15, 0, %0, cr7, cr5, 6  \n"
  61                 /* Set SCTLR[IZ] */
  62                 "mrc    15, 0, %0, cr1, cr0, 0  \n"
  63                 "orr    %0, #0x1800             \n"
  64                 "mcr    15, 0, %0, cr1, cr0, 0  \n"
  65                 "isb    sy                      \n"
  66                 :"=r"(r0));
  67 }
  68
  69 static void spl_init_pfc(void)
  70 {
  71         static const struct reg_config pfc_with_unlock[] = {
  72                 { 0x0090, 0x60000000 },
  73                 { 0x0094, 0x60000000 },
  74                 { 0x0098, 0x00800200 },
  75                 { 0x009c, 0x00000000 },
  76                 { 0x0020, 0x00000000 },
  77                 { 0x0024, 0x00000000 },
  78                 { 0x0028, 0x000244c8 },
  79                 { 0x002c, 0x00000000 },
  80                 { 0x0030, 0x00002400 },
  81                 { 0x0034, 0x01520000 },
  82                 { 0x0038, 0x00724003 },
  83                 { 0x003c, 0x00000000 },
  84                 { 0x0040, 0x00000000 },
  85                 { 0x0044, 0x00000000 },
  86                 { 0x0048, 0x00000000 },
  87                 { 0x004c, 0x00000000 },
  88                 { 0x0050, 0x00000000 },
  89                 { 0x0054, 0x00000000 },
  90                 { 0x0058, 0x00000000 },
  91                 { 0x005c, 0x00000000 },
  92                 { 0x0160, 0x00000000 },
  93                 { 0x0004, 0xffffffff },
  94                 { 0x0008, 0x00ec3fff },
  95                 { 0x000c, 0x3bc001e7 },
  96                 { 0x0010, 0x5bffffff },
  97                 { 0x0014, 0x1ffffffb },
  98                 { 0x0018, 0x01bffff0 },
  99                 { 0x001c, 0xcf7fffff },
 100                 { 0x0074, 0x0381fc00 },
 101         };
 102
 103         static const struct reg_config pfc_without_unlock[] = {
 104                 { 0x0100, 0xffffffdf },
 105                 { 0x0104, 0xc883c3ff },
 106                 { 0x0108, 0x1201f3c9 },
 107                 { 0x010c, 0x00000000 },
 108                 { 0x0110, 0xffffeb04 },
 109                 { 0x0114, 0xc003ffff },
 110                 { 0x0118, 0x0800000f },
 111                 { 0x011c, 0x00187ff0 },
 112         };
 113
 114         static const u32 pfc_base = 0xe6060000;
 115
 116         unsigned int i;
 117
 118         for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
 119                 writel(~pfc_with_unlock[i].val, pfc_base);
 120                 writel(pfc_with_unlock[i].val,
 121                        pfc_base | pfc_with_unlock[i].off);
 122         }
 123
 124         for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
 125                 writel(pfc_without_unlock[i].val,
 126                        pfc_base | pfc_without_unlock[i].off);
 127 }
 128
 129 static void spl_init_gpio(void)
 130 {
 131         static const u16 gpio_offs[] = {
 132                 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
 133         };
 134
 135         static const struct reg_config gpio_set[] = {
 136                 { 0x2000, 0x04381000 },
 137                 { 0x5000, 0x00000000 },
 138                 { 0x5800, 0x000e0000 },
 139         };
 140
 141         static const struct reg_config gpio_clr[] = {
 142                 { 0x1000, 0x00000000 },
 143                 { 0x2000, 0x04381010 },
 144                 { 0x3000, 0x00000000 },
 145                 { 0x4000, 0x00000000 },
 146                 { 0x5000, 0x00400000 },
 147                 { 0x5400, 0x00000000 },
 148                 { 0x5800, 0x000e0380 },
 149         };
 150
 151         static const u32 gpio_base = 0xe6050000;
 152
 153         unsigned int i;
 154
 155         for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
 156                 writel(0, gpio_base | 0x20 | gpio_offs[i]);
 157
 158         for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
 159                 writel(0, gpio_base | 0x00 | gpio_offs[i]);
 160
 161         for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
 162                 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
 163
 164         for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
 165                 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
 166 }
 167
 168 static void spl_init_lbsc(void)
 169 {
 170         static const struct reg_config lbsc_config[] = {
 171                 { 0x00, 0x00000020 },
 172                 { 0x08, 0x00002020 },
 173                 { 0x30, 0x2a103320 },
 174                 { 0x38, 0xff70ff70 },
 175         };
 176
 177         static const u16 lbsc_offs[] = {
 178                 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
 179         };
 180
 181         static const u32 lbsc_base = 0xfec00200;
 182
 183         unsigned int i;
 184
 185         for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
 186                 writel(lbsc_config[i].val,
 187                        lbsc_base | lbsc_config[i].off);
 188                 writel(lbsc_config[i].val,
 189                        lbsc_base | (lbsc_config[i].off + 4));
 190         }
 191
 192         for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
 193                 writel(0, lbsc_base | lbsc_offs[i]);
 194 }
 195
 196 static void spl_init_dbsc(void)
 197 {
 198         static const struct reg_config dbsc_config1[] = {
 199                 { 0x0280, 0x0000a55a },
 200                 { 0x4000, 0x0000a55a },
 201                 { 0x4008, 0x00000001 },
 202                 { 0x0018, 0x21000000 },
 203                 { 0x0018, 0x11000000 },
 204                 { 0x0018, 0x10000000 },
 205                 { 0x0290, 0x00000001 },
 206                 { 0x02a0, 0x80000000 },
 207                 { 0x0290, 0x00000004 },
 208         };
 209
 210         static const struct reg_config dbsc_config2[] = {
 211                 { 0x0290, 0x00000006 },
 212                 { 0x02a0, 0x0001c000 },
 213         };
 214
 215         static const struct reg_config dbsc_config3r0d0[] = {
 216                 { 0x0290, 0x0000000f },
 217                 { 0x02a0, 0x00181885 },
 218                 { 0x0290, 0x00000070 },
 219                 { 0x02a0, 0x7c000887 },
 220                 { 0x0290, 0x00000080 },
 221                 { 0x02a0, 0x7c000887 },
 222                 { 0x0290, 0x00000090 },
 223                 { 0x02a0, 0x7c000887 },
 224                 { 0x0290, 0x000000a0 },
 225                 { 0x02a0, 0x7c000887 },
 226                 { 0x0290, 0x000000b0 },
 227                 { 0x02a0, 0x7c000880 },
 228                 { 0x0290, 0x000000c0 },
 229                 { 0x02a0, 0x7c000880 },
 230                 { 0x0290, 0x000000d0 },
 231                 { 0x02a0, 0x7c000880 },
 232                 { 0x0290, 0x000000e0 },
 233                 { 0x02a0, 0x7c000880 },
 234         };
 235         static const struct reg_config dbsc_config3r0d1[] = {
 236                 { 0x0290, 0x0000000f },
 237                 { 0x02a0, 0x00181885 },
 238                 { 0x0290, 0x00000070 },
 239                 { 0x02a0, 0x7c000887 },
 240                 { 0x0290, 0x00000080 },
 241                 { 0x02a0, 0x7c000887 },
 242                 { 0x0290, 0x00000090 },
 243                 { 0x02a0, 0x7c000887 },
 244                 { 0x0290, 0x000000a0 },
 245                 { 0x02a0, 0x7c000887 },
 246         };
 247
 248         static const struct reg_config dbsc_config3r2[] = {
 249                 { 0x0290, 0x0000000f },
 250                 { 0x02a0, 0x00181224 },
 251         };
 252
 253         static const struct reg_config dbsc_config4[] = {
 254                 { 0x0290, 0x00000010 },
 255                 { 0x02a0, 0xf004649b },
 256                 { 0x0290, 0x00000061 },
 257                 { 0x02a0, 0x0000006d },
 258                 { 0x0290, 0x00000001 },
 259                 { 0x02a0, 0x00000073 },
 260                 { 0x0020, 0x00000007 },
 261                 { 0x0024, 0x0f030a02 },
 262                 { 0x0030, 0x00000001 },
 263                 { 0x00b0, 0x00000000 },
 264                 { 0x0040, 0x0000000b },
 265                 { 0x0044, 0x00000008 },
 266                 { 0x0048, 0x00000000 },
 267                 { 0x0050, 0x0000000b },
 268                 { 0x0054, 0x000c000b },
 269                 { 0x0058, 0x00000027 },
 270                 { 0x005c, 0x0000001c },
 271                 { 0x0060, 0x00000006 },
 272                 { 0x0064, 0x00000020 },
 273                 { 0x0068, 0x00000008 },
 274                 { 0x006c, 0x0000000c },
 275                 { 0x0070, 0x00000009 },
 276                 { 0x0074, 0x00000012 },
 277                 { 0x0078, 0x000000d0 },
 278                 { 0x007c, 0x00140005 },
 279                 { 0x0080, 0x00050004 },
 280                 { 0x0084, 0x70233005 },
 281                 { 0x0088, 0x000c0000 },
 282                 { 0x008c, 0x00000200 },
 283                 { 0x0090, 0x00000040 },
 284                 { 0x0100, 0x00000001 },
 285                 { 0x00c0, 0x00020001 },
 286                 { 0x00c8, 0x20042004 },
 287                 { 0x0380, 0x00020002 },
 288                 { 0x0390, 0x0000001f },
 289         };
 290
 291         static const struct reg_config dbsc_config5[] = {
 292                 { 0x0244, 0x00000011 },
 293                 { 0x0290, 0x00000003 },
 294                 { 0x02a0, 0x0300c561 },
 295                 { 0x0290, 0x00000023 },
 296                 { 0x02a0, 0x00fcdb60 },
 297                 { 0x0290, 0x00000011 },
 298                 { 0x02a0, 0x1000040b },
 299                 { 0x0290, 0x00000012 },
 300                 { 0x02a0, 0x9d9cbb66 },
 301                 { 0x0290, 0x00000013 },
 302                 { 0x02a0, 0x1a868400 },
 303                 { 0x0290, 0x00000014 },
 304                 { 0x02a0, 0x300214d8 },
 305                 { 0x0290, 0x00000015 },
 306                 { 0x02a0, 0x00000d70 },
 307                 { 0x0290, 0x00000016 },
 308                 { 0x02a0, 0x00000006 },
 309                 { 0x0290, 0x00000017 },
 310                 { 0x02a0, 0x00000018 },
 311                 { 0x0290, 0x0000001a },
 312                 { 0x02a0, 0x910035c7 },
 313                 { 0x0290, 0x00000004 },
 314         };
 315
 316         static const struct reg_config dbsc_config6[] = {
 317                 { 0x0290, 0x00000001 },
 318                 { 0x02a0, 0x00000181 },
 319                 { 0x0018, 0x11000000 },
 320                 { 0x0290, 0x00000004 },
 321         };
 322
 323         static const struct reg_config dbsc_config7[] = {
 324                 { 0x0290, 0x00000001 },
 325                 { 0x02a0, 0x0000fe01 },
 326                 { 0x0304, 0x00000000 },
 327                 { 0x00f4, 0x01004c20 },
 328                 { 0x00f8, 0x014a00b9 },
 329                 { 0x00e0, 0x00000140 },
 330                 { 0x00e4, 0x00081860 },
 331                 { 0x00e8, 0x00010000 },
 332                 { 0x0290, 0x00000004 },
 333         };
 334
 335         static const struct reg_config dbsc_config8[] = {
 336                 { 0x0014, 0x00000001 },
 337                 { 0x0290, 0x00000010 },
 338                 { 0x02a0, 0xf00464db },
 339                 { 0x4008, 0x00000000 },
 340                 { 0x4000, 0x00000000 },
 341                 { 0x0010, 0x00000001 },
 342                 { 0x0280, 0x00000000 },
 343         };
 344
 345         static const u32 dbsc3_0_base = DBSC3_0_BASE;
 346         static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
 347         static const u32 prr_base = 0xff000044;
 348         const u16 prr_rev = readl(prr_base) & 0x7fff;
 349         unsigned int i;
 350
 351         for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
 352                 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
 353                 writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
 354         }
 355
 356         dbsc_wait(0x2a0);
 357
 358         for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
 359                 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
 360                 writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
 361         }
 362
 363         if (prr_rev == 0x4700) {
 364                 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
 365                         writel(dbsc_config3r0d0[i].val,
 366                                 dbsc3_0_base | dbsc_config3r0d0[i].off);
 367                 }
 368                 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
 369                         writel(dbsc_config3r0d1[i].val,
 370                                 dbsc3_1_base | dbsc_config3r0d1[i].off);
 371                 }
 372         } else if (prr_rev != 0x4710) {
 373                 for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
 374                         writel(dbsc_config3r2[i].val,
 375                                 dbsc3_0_base | dbsc_config3r2[i].off);
 376                         writel(dbsc_config3r2[i].val,
 377                                 dbsc3_1_base | dbsc_config3r2[i].off);
 378                 }
 379         }
 380
 381         for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
 382                 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
 383                 writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
 384         }
 385
 386         dbsc_wait(0x240);
 387
 388         for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
 389                 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
 390                 writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
 391         }
 392
 393         dbsc_wait(0x2a0);
 394
 395         for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
 396                 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
 397                 writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
 398         }
 399
 400         dbsc_wait(0x2a0);
 401
 402         for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
 403                 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
 404                 writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
 405         }
 406
 407         dbsc_wait(0x2a0);
 408
 409         for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
 410                 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
 411                 writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
 412         }
 413
 414 }
 415
 416 static void spl_init_qspi(void)
 417 {
 418         mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
 419
 420         static const u32 qspi_base = 0xe6b10000;
 421
 422         writeb(0x08, qspi_base + 0x00);
 423         writeb(0x00, qspi_base + 0x01);
 424         writeb(0x06, qspi_base + 0x02);
 425         writeb(0x01, qspi_base + 0x0a);
 426         writeb(0x00, qspi_base + 0x0b);
 427         writeb(0x00, qspi_base + 0x0c);
 428         writeb(0x00, qspi_base + 0x0d);
 429         writeb(0x00, qspi_base + 0x0e);
 430
 431         writew(0xe080, qspi_base + 0x10);
 432
 433         writeb(0xc0, qspi_base + 0x18);
 434         writeb(0x00, qspi_base + 0x18);
 435         writeb(0x00, qspi_base + 0x08);
 436         writeb(0x48, qspi_base + 0x00);
 437 }
 438
 439 void board_init_f(ulong dummy)
 440 {
 441         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 442         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
 443
 444         /*
 445          * SD0 clock is set to 97.5MHz by default.
 446          * Set SD2 to the 97.5MHz as well.
 447          */
 448         writel(SD_97500KHZ, SD2CKCR);
 449
 450         spl_init_sys();
 451         spl_init_pfc();
 452         spl_init_gpio();
 453         spl_init_lbsc();
 454         spl_init_dbsc();
 455         spl_init_qspi();
 456 }
 457
 458 void spl_board_init(void)
 459 {
 460         /* UART clocks enabled and gd valid - init serial console */
 461         preloader_console_init();
 462 }
 463
 464 void board_boot_order(u32 *spl_boot_list)
 465 {
 466         const u32 jtag_magic = 0x1337c0de;
 467         const u32 load_magic = 0xb33fc0de;
 468
 469         /*
 470          * If JTAG probe sets special word at 0xe6300020, then it must
 471          * put U-Boot into RAM and SPL will start it from RAM.
 472          */
 473         if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
 474                 printf("JTAG boot detected!\n");
 475
 476                 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
 477                         ;
 478
 479                 spl_boot_list[0] = BOOT_DEVICE_RAM;
 480                 spl_boot_list[1] = BOOT_DEVICE_NONE;
 481
 482                 return;
 483         }
 484
 485         /* Boot from SPI NOR with YMODEM UART fallback. */
 486         spl_boot_list[0] = BOOT_DEVICE_SPI;
 487         spl_boot_list[1] = BOOT_DEVICE_UART;
 488         spl_boot_list[2] = BOOT_DEVICE_NONE;
 489 }
 490
 491 void reset_cpu(ulong addr)
 492 {
 493 }