1 // SPDX-License-Identifier: GPL-2.0
3 * board/renesas/lager/lager.c
4 * This file is lager board support.
6 * Copyright (C) 2013 Renesas Electronics Corporation
7 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
11 #include <clock_legacy.h>
14 #include <env_internal.h>
20 #include <asm/global_data.h>
21 #include <dm/platform_data/serial_sh.h>
22 #include <asm/processor.h>
23 #include <asm/mach-types.h>
25 #include <linux/bitops.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/rmobile.h>
31 #include <asm/arch/rcar-mstp.h>
32 #include <asm/arch/mmc.h>
33 #include <asm/arch/sh_sdhi.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #define CLK2MHZ(clk) (clk / 1000 / 1000)
44 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
45 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
48 writel(0xA5A5A500, &rwdt->rwtcsra);
49 writel(0xA5A5A500, &swdt->swtcsra);
51 /* CPU frequency setting. Set to 1.4GHz */
52 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
54 u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
56 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
59 stat = readl(PLLECR) & PLL0ST;
60 } while (stat == 0x0);
63 /* QoS(Quality-of-Service) Init */
67 #define TMU0_MSTP125 BIT(25)
69 #define SD1CKCR 0xE6150078
70 #define SD2CKCR 0xE615026C
71 #define SD_97500KHZ 0x7
73 int board_early_init_f(void)
75 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
78 * SD0 clock is set to 97.5MHz by default.
79 * Set SD1 and SD2 to the 97.5MHz as well.
81 writel(SD_97500KHZ, SD1CKCR);
82 writel(SD_97500KHZ, SD2CKCR);
87 #define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */
91 /* adress of boot parameters */
92 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
94 /* Force ethernet PHY out of reset */
95 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
96 gpio_direction_output(ETHERNET_PHY_RESET, 0);
98 gpio_direction_output(ETHERNET_PHY_RESET, 1);
105 if (fdtdec_setup_mem_size_base() != 0)
111 int dram_init_banksize(void)
113 fdtdec_setup_memory_banksize();
119 #define PHY_CONTROL1 0x1E
120 #define PHY_LED_MODE 0xC000
121 #define PHY_LED_MODE_ACK 0x4000
122 int board_phy_config(struct phy_device *phydev)
124 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
125 ret &= ~PHY_LED_MODE;
126 ret |= PHY_LED_MODE_ACK;
127 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
135 const u8 pmic_bus = 2;
136 const u8 pmic_addr = 0x58;
140 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
144 ret = dm_i2c_read(dev, 0x13, &data, 1);
150 ret = dm_i2c_write(dev, 0x13, &data, 1);
155 enum env_location env_get_location(enum env_operation op, int prio)
157 const u32 load_magic = 0xb33fc0de;
159 /* Block environment access if loaded using JTAG */
160 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
167 return ENVL_SPI_FLASH;