1 // SPDX-License-Identifier: GPL-2.0+
3 * board/renesas/ebisu/ebisu.c
4 * This file is Ebisu board support.
6 * Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com>
13 #include <dm/platform_data/serial_sh.h>
14 #include <asm/processor.h>
15 #include <asm/mach-types.h>
17 #include <linux/errno.h>
18 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/rmobile.h>
22 #include <asm/arch/rcar-mstp.h>
23 #include <asm/arch/sh_sdhi.h>
27 DECLARE_GLOBAL_DATA_PTR;
33 #define TMU0_MSTP125 BIT(25) /* secure */
35 int board_early_init_f(void)
38 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
45 /* adress of boot parameters */
46 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
53 if (fdtdec_setup_mem_size_base() != 0)
59 int dram_init_banksize(void)
61 fdtdec_setup_memory_banksize();
66 #define RST_BASE 0xE6160000
67 #define RST_CA57RESCNT (RST_BASE + 0x40)
68 #define RST_CA53RESCNT (RST_BASE + 0x44)
69 #define RST_RSTOUTCR (RST_BASE + 0x58)
70 #define RST_CA57_CODE 0xA5A5000F
71 #define RST_CA53_CODE 0x5A5A000F
73 void reset_cpu(ulong addr)
75 unsigned long midr, cputype;
77 asm volatile("mrs %0, midr_el1" : "=r" (midr));
78 cputype = (midr >> 4) & 0xfff;
81 writel(RST_CA53_CODE, RST_CA53RESCNT);
82 else if (cputype == 0xd07)
83 writel(RST_CA57_CODE, RST_CA57RESCNT);