1 // SPDX-License-Identifier: GPL-2.0+
3 * board/renesas/draak/draak.c
4 * This file is Draak board support.
6 * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
15 #include <dm/platform_data/serial_sh.h>
16 #include <asm/processor.h>
17 #include <asm/mach-types.h>
19 #include <linux/errno.h>
20 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/rmobile.h>
24 #include <asm/arch/rcar-mstp.h>
25 #include <asm/arch/sh_sdhi.h>
29 DECLARE_GLOBAL_DATA_PTR;
35 #define GSX_MSTP112 BIT(12) /* 3DG */
36 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */
37 #define DVFS_MSTP926 BIT(26)
38 #define HSUSB_MSTP704 BIT(4) /* HSUSB */
40 int board_early_init_f(void)
42 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
44 mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
49 /* HSUSB block registers */
50 #define HSUSB_REG_LPSTS 0xE6590102
51 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
52 #define HSUSB_REG_UGCTRL2 0xE6590184
53 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
54 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
58 /* adress of boot parameters */
59 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
62 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
64 /* Configure the HSUSB block */
65 mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
67 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
68 HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
69 /* low power status */
70 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
75 #define RST_BASE 0xE6160000
76 #define RST_CA57RESCNT (RST_BASE + 0x40)
77 #define RST_CA53RESCNT (RST_BASE + 0x44)
78 #define RST_RSTOUTCR (RST_BASE + 0x58)
79 #define RST_CA57_CODE 0xA5A5000F
80 #define RST_CA53_CODE 0x5A5A000F
82 void reset_cpu(ulong addr)
84 unsigned long midr, cputype;
86 asm volatile("mrs %0, midr_el1" : "=r" (midr));
87 cputype = (midr >> 4) & 0xfff;
90 writel(RST_CA53_CODE, RST_CA53RESCNT);
91 else if (cputype == 0xd07)
92 writel(RST_CA57_CODE, RST_CA57RESCNT);