1 // SPDX-License-Identifier: GPL-2.0+
3 * board/renesas/draak/draak.c
4 * This file is Draak board support.
6 * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
16 #include <dm/platform_data/serial_sh.h>
17 #include <asm/processor.h>
18 #include <asm/mach-types.h>
20 #include <linux/errno.h>
21 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/rmobile.h>
25 #include <asm/arch/rcar-mstp.h>
26 #include <asm/arch/sh_sdhi.h>
30 DECLARE_GLOBAL_DATA_PTR;
36 #define GSX_MSTP112 BIT(12) /* 3DG */
37 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */
38 #define DVFS_MSTP926 BIT(26)
39 #define HSUSB_MSTP704 BIT(4) /* HSUSB */
41 int board_early_init_f(void)
43 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
45 mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
50 /* HSUSB block registers */
51 #define HSUSB_REG_LPSTS 0xE6590102
52 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
53 #define HSUSB_REG_UGCTRL2 0xE6590184
54 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
55 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
59 /* adress of boot parameters */
60 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
63 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
65 /* Configure the HSUSB block */
66 mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
68 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
69 HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
70 /* low power status */
71 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
76 #define RST_BASE 0xE6160000
77 #define RST_CA57RESCNT (RST_BASE + 0x40)
78 #define RST_CA53RESCNT (RST_BASE + 0x44)
79 #define RST_RSTOUTCR (RST_BASE + 0x58)
80 #define RST_CA57_CODE 0xA5A5000F
81 #define RST_CA53_CODE 0x5A5A000F
83 void reset_cpu(ulong addr)
85 unsigned long midr, cputype;
87 asm volatile("mrs %0, midr_el1" : "=r" (midr));
88 cputype = (midr >> 4) & 0xfff;
91 writel(RST_CA53_CODE, RST_CA53RESCNT);
92 else if (cputype == 0xd07)
93 writel(RST_CA57_CODE, RST_CA57RESCNT);