board/renesas/blanche/blanche.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * board/renesas/blanche/blanche.c
   4  *     This file is blanche board support.
   5  *
   6  * Copyright (C) 2016 Renesas Electronics Corporation
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <asm/arch/mmc.h>
  12 #include <asm/arch/rcar-mstp.h>
  13 #include <asm/arch/rmobile.h>
  14 #include <asm/arch/sh_sdhi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/io.h>
  18 #include <asm/mach-types.h>
  19 #include <asm/processor.h>
  20 #include <dm.h>
  21 #include <dm/platform_data/serial_sh.h>
  22 #include <env.h>
  23 #include <hang.h>
  24 #include <i2c.h>
  25 #include <linux/errno.h>
  26 #include <malloc.h>
  27 #include <miiphy.h>
  28 #include <mmc.h>
  29 #include <netdev.h>
  30 #include "qos.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define CPG_PLL1CR      0xE6150028
  35 #define CPG_PLL3CR      0xE61500DC
  36
  37 #define TMU0_MSTP125    BIT(25)
  38 #define QSPI_MSTP917    BIT(17)
  39
  40 struct reg_config {
  41         u16     off;
  42         u32     val;
  43 };
  44
  45 static void blanche_init_sys(void)
  46 {
  47         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  48         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  49         u32 cpu_type;
  50
  51         cpu_type = rmobile_get_cpu_type();
  52         if (cpu_type == 0x4A) {
  53                 writel(0x4D000000, CPG_PLL1CR);
  54                 writel(0x4F000000, CPG_PLL3CR);
  55         }
  56
  57         /* Watchdog init */
  58         writel(0xA5A5A500, &rwdt->rwtcsra);
  59         writel(0xA5A5A500, &swdt->swtcsra);
  60 }
  61
  62 static void blanche_init_pfc(void)
  63 {
  64         static const struct reg_config pfc_with_unlock[] = {
  65                 { 0x0004, 0x0bffffff },
  66                 { 0x0008, 0x002fffff },
  67                 { 0x0014, 0x00000fff },
  68                 { 0x0018, 0x00010fff },
  69                 { 0x001c, 0x00010fff },
  70                 { 0x0020, 0x00010fff },
  71                 { 0x0024, 0x00010fff },
  72                 { 0x0028, 0x00010fff },
  73                 { 0x002c, 0x04006000 },
  74                 { 0x0030, 0x303fefe0 },
  75                 { 0x0058, 0x0002000e },
  76         };
  77
  78         static const struct reg_config pfc_without_unlock[] = {
  79                 { 0x0108, 0x00000000 },
  80                 { 0x010c, 0x0803FF40 },
  81                 { 0x0110, 0x0000FFFF },
  82                 { 0x0114, 0x00010FFF },
  83                 { 0x011c, 0x0001AFFF },
  84                 { 0x0124, 0x0001CFFF },
  85                 { 0x0128, 0xC0438001 },
  86                 { 0x012c, 0x0FC00007 },
  87         };
  88
  89         static const u32 pfc_base = 0xe6060000;
  90
  91         unsigned int i;
  92
  93         for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
  94                 writel(~pfc_with_unlock[i].val, pfc_base);
  95                 writel(pfc_with_unlock[i].val,
  96                        pfc_base | pfc_with_unlock[i].off);
  97         }
  98
  99         for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
 100                 writel(pfc_without_unlock[i].val,
 101                        pfc_base | pfc_without_unlock[i].off);
 102 }
 103
 104 static void blanche_init_lbsc(void)
 105 {
 106         static const struct reg_config lbsc_config[] = {
 107                 { 0x00, 0x00000020 },
 108                 { 0x08, 0x00002020 },
 109                 { 0x30, 0x2a103320 },
 110                 { 0x38, 0x19102110 },
 111         };
 112
 113         static const u32 lbsc_base = 0xfec00200;
 114
 115         unsigned int i;
 116
 117         for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
 118                 writel(lbsc_config[i].val,
 119                        lbsc_base | lbsc_config[i].off);
 120                 writel(lbsc_config[i].val,
 121                        lbsc_base | (lbsc_config[i].off + 4));
 122         }
 123 }
 124
 125 #if defined(CONFIG_MTD_NOR_FLASH)
 126 static void dbsc_wait(u16 reg)
 127 {
 128         static const u32 dbsc3_0_base = DBSC3_0_BASE;
 129
 130         while (!(readl(dbsc3_0_base + reg) & BIT(0)))
 131                 ;
 132 }
 133
 134 static void blanche_init_dbsc(void)
 135 {
 136         static const struct reg_config dbsc_config1[] = {
 137                 { 0x0280, 0x0000a55a },
 138                 { 0x0018, 0x21000000 },
 139                 { 0x0018, 0x11000000 },
 140                 { 0x0018, 0x10000000 },
 141                 { 0x0290, 0x00000001 },
 142                 { 0x02a0, 0x80000000 },
 143                 { 0x0290, 0x00000004 },
 144         };
 145
 146         static const struct reg_config dbsc_config2[] = {
 147                 { 0x0290, 0x00000006 },
 148                 { 0x02a0, 0x0001c000 },
 149         };
 150
 151         static const struct reg_config dbsc_config4[] = {
 152                 { 0x0290, 0x0000000f },
 153                 { 0x02a0, 0x00181ee4 },
 154                 { 0x0290, 0x00000010 },
 155                 { 0x02a0, 0xf00464db },
 156                 { 0x0290, 0x00000061 },
 157                 { 0x02a0, 0x0000008d },
 158                 { 0x0290, 0x00000001 },
 159                 { 0x02a0, 0x00000073 },
 160                 { 0x0020, 0x00000007 },
 161                 { 0x0024, 0x0f030a02 },
 162                 { 0x0030, 0x00000001 },
 163                 { 0x00b0, 0x00000000 },
 164                 { 0x0040, 0x0000000b },
 165                 { 0x0044, 0x00000008 },
 166                 { 0x0048, 0x00000000 },
 167                 { 0x0050, 0x0000000b },
 168                 { 0x0054, 0x000c000b },
 169                 { 0x0058, 0x00000027 },
 170                 { 0x005c, 0x0000001c },
 171                 { 0x0060, 0x00000006 },
 172                 { 0x0064, 0x00000020 },
 173                 { 0x0068, 0x00000008 },
 174                 { 0x006c, 0x0000000c },
 175                 { 0x0070, 0x00000009 },
 176                 { 0x0074, 0x00000012 },
 177                 { 0x0078, 0x000000d0 },
 178                 { 0x007c, 0x00140005 },
 179                 { 0x0080, 0x00050004 },
 180                 { 0x0084, 0x70233005 },
 181                 { 0x0088, 0x000c0000 },
 182                 { 0x008c, 0x00000300 },
 183                 { 0x0090, 0x00000040 },
 184                 { 0x0100, 0x00000001 },
 185                 { 0x00c0, 0x00020001 },
 186                 { 0x00c8, 0x20082004 },
 187                 { 0x0380, 0x00020002 },
 188                 { 0x0390, 0x0000001f },
 189         };
 190
 191         static const struct reg_config dbsc_config5[] = {
 192                 { 0x0244, 0x00000011 },
 193                 { 0x0290, 0x00000003 },
 194                 { 0x02a0, 0x0300c4e1 },
 195                 { 0x0290, 0x00000023 },
 196                 { 0x02a0, 0x00fcdb60 },
 197                 { 0x0290, 0x00000011 },
 198                 { 0x02a0, 0x1000040b },
 199                 { 0x0290, 0x00000012 },
 200                 { 0x02a0, 0x9d9cbb66 },
 201                 { 0x0290, 0x00000013 },
 202                 { 0x02a0, 0x1a868400 },
 203                 { 0x0290, 0x00000014 },
 204                 { 0x02a0, 0x300214d8 },
 205                 { 0x0290, 0x00000015 },
 206                 { 0x02a0, 0x00000d70 },
 207                 { 0x0290, 0x00000016 },
 208                 { 0x02a0, 0x00000004 },
 209                 { 0x0290, 0x00000017 },
 210                 { 0x02a0, 0x00000018 },
 211                 { 0x0290, 0x0000001a },
 212                 { 0x02a0, 0x910035c7 },
 213                 { 0x0290, 0x00000004 },
 214         };
 215
 216         static const struct reg_config dbsc_config6[] = {
 217                 { 0x0290, 0x00000001 },
 218                 { 0x02a0, 0x00000181 },
 219                 { 0x0018, 0x11000000 },
 220                 { 0x0290, 0x00000004 },
 221         };
 222
 223         static const struct reg_config dbsc_config7[] = {
 224                 { 0x0290, 0x00000001 },
 225                 { 0x02a0, 0x0000fe01 },
 226                 { 0x0304, 0x00000000 },
 227                 { 0x00f4, 0x01004c20 },
 228                 { 0x00f8, 0x014000aa },
 229                 { 0x00e0, 0x00000140 },
 230                 { 0x00e4, 0x00081860 },
 231                 { 0x00e8, 0x00010000 },
 232                 { 0x0290, 0x00000004 },
 233         };
 234
 235         static const struct reg_config dbsc_config8[] = {
 236                 { 0x0014, 0x00000001 },
 237                 { 0x0010, 0x00000001 },
 238                 { 0x0280, 0x00000000 },
 239         };
 240
 241         static const u32 dbsc3_0_base = DBSC3_0_BASE;
 242         unsigned int i;
 243
 244         for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
 245                 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
 246
 247         dbsc_wait(0x2a0);
 248
 249         for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
 250                 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
 251
 252         for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
 253                 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
 254
 255         dbsc_wait(0x240);
 256
 257         for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
 258                 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
 259
 260         dbsc_wait(0x2a0);
 261
 262         for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
 263                 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
 264
 265         dbsc_wait(0x2a0);
 266
 267         for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
 268                 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
 269
 270         dbsc_wait(0x2a0);
 271
 272         for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
 273                 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
 274
 275 }
 276
 277 static void s_init_wait(volatile unsigned int cnt)
 278 {
 279         volatile u32 i = cnt * 0x10000;
 280
 281         while (i-- > 0)
 282                 ;
 283 }
 284 #endif
 285
 286 void s_init(void)
 287 {
 288         blanche_init_sys();
 289         qos_init();
 290         blanche_init_pfc();
 291         blanche_init_lbsc();
 292 #if defined(CONFIG_MTD_NOR_FLASH)
 293         s_init_wait(10);
 294         blanche_init_dbsc();
 295 #endif /* CONFIG_MTD_NOR_FLASH */
 296 }
 297
 298 int board_early_init_f(void)
 299 {
 300         /* TMU0 */
 301         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 302         /* QSPI */
 303         mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
 304
 305         return 0;
 306 }
 307
 308 int board_init(void)
 309 {
 310         /* adress of boot parameters */
 311         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 312
 313         return 0;
 314 }
 315
 316 /* Added for BLANCHE(R-CarV2H board) */
 317 int board_eth_init(bd_t *bis)
 318 {
 319         int rc = 0;
 320
 321 #ifdef CONFIG_SMC911X
 322         struct eth_device *dev;
 323         uchar eth_addr[6];
 324
 325         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 326
 327         if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
 328                 dev = eth_get_dev_by_index(0);
 329                 if (dev) {
 330                         eth_env_set_enetaddr("ethaddr", dev->enetaddr);
 331                 } else {
 332                         printf("blanche: Couldn't get eth device\n");
 333                         rc = -1;
 334                 }
 335         }
 336
 337 #endif
 338
 339         return rc;
 340 }
 341
 342 int dram_init(void)
 343 {
 344         if (fdtdec_setup_mem_size_base() != 0)
 345                 return -EINVAL;
 346
 347         return 0;
 348 }
 349
 350 int dram_init_banksize(void)
 351 {
 352         fdtdec_setup_memory_banksize();
 353
 354         return 0;
 355 }
 356
 357 void reset_cpu(ulong addr)
 358 {
 359         struct udevice *dev;
 360         const u8 pmic_bus = 6;
 361         const u8 pmic_addr = 0x58;
 362         u8 data;
 363         int ret;
 364
 365         ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
 366         if (ret)
 367                 hang();
 368
 369         ret = dm_i2c_read(dev, 0x13, &data, 1);
 370         if (ret)
 371                 hang();
 372
 373         data |= BIT(1);
 374
 375         ret = dm_i2c_write(dev, 0x13, &data, 1);
 376         if (ret)
 377                 hang();
 378 }