board/renesas/blanche/blanche.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * board/renesas/blanche/blanche.c
   4  *     This file is blanche board support.
   5  *
   6  * Copyright (C) 2016 Renesas Electronics Corporation
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <init.h>
  12 #include <net.h>
  13 #include <asm/arch/mmc.h>
  14 #include <asm/arch/rcar-mstp.h>
  15 #include <asm/arch/rmobile.h>
  16 #include <asm/arch/sh_sdhi.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/mach-types.h>
  21 #include <asm/processor.h>
  22 #include <dm.h>
  23 #include <dm/platform_data/serial_sh.h>
  24 #include <env.h>
  25 #include <hang.h>
  26 #include <i2c.h>
  27 #include <linux/errno.h>
  28 #include <malloc.h>
  29 #include <miiphy.h>
  30 #include <mmc.h>
  31 #include <netdev.h>
  32 #include "qos.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define CPG_PLL1CR      0xE6150028
  37 #define CPG_PLL3CR      0xE61500DC
  38
  39 #define TMU0_MSTP125    BIT(25)
  40 #define QSPI_MSTP917    BIT(17)
  41
  42 struct reg_config {
  43         u16     off;
  44         u32     val;
  45 };
  46
  47 static void blanche_init_sys(void)
  48 {
  49         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  50         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  51         u32 cpu_type;
  52
  53         cpu_type = rmobile_get_cpu_type();
  54         if (cpu_type == 0x4A) {
  55                 writel(0x4D000000, CPG_PLL1CR);
  56                 writel(0x4F000000, CPG_PLL3CR);
  57         }
  58
  59         /* Watchdog init */
  60         writel(0xA5A5A500, &rwdt->rwtcsra);
  61         writel(0xA5A5A500, &swdt->swtcsra);
  62 }
  63
  64 static void blanche_init_pfc(void)
  65 {
  66         static const struct reg_config pfc_with_unlock[] = {
  67                 { 0x0004, 0x0bffffff },
  68                 { 0x0008, 0x002fffff },
  69                 { 0x0014, 0x00000fff },
  70                 { 0x0018, 0x00010fff },
  71                 { 0x001c, 0x00010fff },
  72                 { 0x0020, 0x00010fff },
  73                 { 0x0024, 0x00010fff },
  74                 { 0x0028, 0x00010fff },
  75                 { 0x002c, 0x04006000 },
  76                 { 0x0030, 0x303fefe0 },
  77                 { 0x0058, 0x0002000e },
  78         };
  79
  80         static const struct reg_config pfc_without_unlock[] = {
  81                 { 0x0108, 0x00000000 },
  82                 { 0x010c, 0x0803FF40 },
  83                 { 0x0110, 0x0000FFFF },
  84                 { 0x0114, 0x00010FFF },
  85                 { 0x011c, 0x0001AFFF },
  86                 { 0x0124, 0x0001CFFF },
  87                 { 0x0128, 0xC0438001 },
  88                 { 0x012c, 0x0FC00007 },
  89         };
  90
  91         static const u32 pfc_base = 0xe6060000;
  92
  93         unsigned int i;
  94
  95         for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
  96                 writel(~pfc_with_unlock[i].val, pfc_base);
  97                 writel(pfc_with_unlock[i].val,
  98                        pfc_base | pfc_with_unlock[i].off);
  99         }
 100
 101         for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
 102                 writel(pfc_without_unlock[i].val,
 103                        pfc_base | pfc_without_unlock[i].off);
 104 }
 105
 106 static void blanche_init_lbsc(void)
 107 {
 108         static const struct reg_config lbsc_config[] = {
 109                 { 0x00, 0x00000020 },
 110                 { 0x08, 0x00002020 },
 111                 { 0x30, 0x2a103320 },
 112                 { 0x38, 0x19102110 },
 113         };
 114
 115         static const u32 lbsc_base = 0xfec00200;
 116
 117         unsigned int i;
 118
 119         for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
 120                 writel(lbsc_config[i].val,
 121                        lbsc_base | lbsc_config[i].off);
 122                 writel(lbsc_config[i].val,
 123                        lbsc_base | (lbsc_config[i].off + 4));
 124         }
 125 }
 126
 127 #if defined(CONFIG_MTD_NOR_FLASH)
 128 static void dbsc_wait(u16 reg)
 129 {
 130         static const u32 dbsc3_0_base = DBSC3_0_BASE;
 131
 132         while (!(readl(dbsc3_0_base + reg) & BIT(0)))
 133                 ;
 134 }
 135
 136 static void blanche_init_dbsc(void)
 137 {
 138         static const struct reg_config dbsc_config1[] = {
 139                 { 0x0280, 0x0000a55a },
 140                 { 0x0018, 0x21000000 },
 141                 { 0x0018, 0x11000000 },
 142                 { 0x0018, 0x10000000 },
 143                 { 0x0290, 0x00000001 },
 144                 { 0x02a0, 0x80000000 },
 145                 { 0x0290, 0x00000004 },
 146         };
 147
 148         static const struct reg_config dbsc_config2[] = {
 149                 { 0x0290, 0x00000006 },
 150                 { 0x02a0, 0x0001c000 },
 151         };
 152
 153         static const struct reg_config dbsc_config4[] = {
 154                 { 0x0290, 0x0000000f },
 155                 { 0x02a0, 0x00181ee4 },
 156                 { 0x0290, 0x00000010 },
 157                 { 0x02a0, 0xf00464db },
 158                 { 0x0290, 0x00000061 },
 159                 { 0x02a0, 0x0000008d },
 160                 { 0x0290, 0x00000001 },
 161                 { 0x02a0, 0x00000073 },
 162                 { 0x0020, 0x00000007 },
 163                 { 0x0024, 0x0f030a02 },
 164                 { 0x0030, 0x00000001 },
 165                 { 0x00b0, 0x00000000 },
 166                 { 0x0040, 0x0000000b },
 167                 { 0x0044, 0x00000008 },
 168                 { 0x0048, 0x00000000 },
 169                 { 0x0050, 0x0000000b },
 170                 { 0x0054, 0x000c000b },
 171                 { 0x0058, 0x00000027 },
 172                 { 0x005c, 0x0000001c },
 173                 { 0x0060, 0x00000006 },
 174                 { 0x0064, 0x00000020 },
 175                 { 0x0068, 0x00000008 },
 176                 { 0x006c, 0x0000000c },
 177                 { 0x0070, 0x00000009 },
 178                 { 0x0074, 0x00000012 },
 179                 { 0x0078, 0x000000d0 },
 180                 { 0x007c, 0x00140005 },
 181                 { 0x0080, 0x00050004 },
 182                 { 0x0084, 0x70233005 },
 183                 { 0x0088, 0x000c0000 },
 184                 { 0x008c, 0x00000300 },
 185                 { 0x0090, 0x00000040 },
 186                 { 0x0100, 0x00000001 },
 187                 { 0x00c0, 0x00020001 },
 188                 { 0x00c8, 0x20082004 },
 189                 { 0x0380, 0x00020002 },
 190                 { 0x0390, 0x0000001f },
 191         };
 192
 193         static const struct reg_config dbsc_config5[] = {
 194                 { 0x0244, 0x00000011 },
 195                 { 0x0290, 0x00000003 },
 196                 { 0x02a0, 0x0300c4e1 },
 197                 { 0x0290, 0x00000023 },
 198                 { 0x02a0, 0x00fcdb60 },
 199                 { 0x0290, 0x00000011 },
 200                 { 0x02a0, 0x1000040b },
 201                 { 0x0290, 0x00000012 },
 202                 { 0x02a0, 0x9d9cbb66 },
 203                 { 0x0290, 0x00000013 },
 204                 { 0x02a0, 0x1a868400 },
 205                 { 0x0290, 0x00000014 },
 206                 { 0x02a0, 0x300214d8 },
 207                 { 0x0290, 0x00000015 },
 208                 { 0x02a0, 0x00000d70 },
 209                 { 0x0290, 0x00000016 },
 210                 { 0x02a0, 0x00000004 },
 211                 { 0x0290, 0x00000017 },
 212                 { 0x02a0, 0x00000018 },
 213                 { 0x0290, 0x0000001a },
 214                 { 0x02a0, 0x910035c7 },
 215                 { 0x0290, 0x00000004 },
 216         };
 217
 218         static const struct reg_config dbsc_config6[] = {
 219                 { 0x0290, 0x00000001 },
 220                 { 0x02a0, 0x00000181 },
 221                 { 0x0018, 0x11000000 },
 222                 { 0x0290, 0x00000004 },
 223         };
 224
 225         static const struct reg_config dbsc_config7[] = {
 226                 { 0x0290, 0x00000001 },
 227                 { 0x02a0, 0x0000fe01 },
 228                 { 0x0304, 0x00000000 },
 229                 { 0x00f4, 0x01004c20 },
 230                 { 0x00f8, 0x014000aa },
 231                 { 0x00e0, 0x00000140 },
 232                 { 0x00e4, 0x00081860 },
 233                 { 0x00e8, 0x00010000 },
 234                 { 0x0290, 0x00000004 },
 235         };
 236
 237         static const struct reg_config dbsc_config8[] = {
 238                 { 0x0014, 0x00000001 },
 239                 { 0x0010, 0x00000001 },
 240                 { 0x0280, 0x00000000 },
 241         };
 242
 243         static const u32 dbsc3_0_base = DBSC3_0_BASE;
 244         unsigned int i;
 245
 246         for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
 247                 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
 248
 249         dbsc_wait(0x2a0);
 250
 251         for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
 252                 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
 253
 254         for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
 255                 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
 256
 257         dbsc_wait(0x240);
 258
 259         for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
 260                 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
 261
 262         dbsc_wait(0x2a0);
 263
 264         for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
 265                 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
 266
 267         dbsc_wait(0x2a0);
 268
 269         for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
 270                 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
 271
 272         dbsc_wait(0x2a0);
 273
 274         for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
 275                 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
 276
 277 }
 278
 279 static void s_init_wait(volatile unsigned int cnt)
 280 {
 281         volatile u32 i = cnt * 0x10000;
 282
 283         while (i-- > 0)
 284                 ;
 285 }
 286 #endif
 287
 288 void s_init(void)
 289 {
 290         blanche_init_sys();
 291         qos_init();
 292         blanche_init_pfc();
 293         blanche_init_lbsc();
 294 #if defined(CONFIG_MTD_NOR_FLASH)
 295         s_init_wait(10);
 296         blanche_init_dbsc();
 297 #endif /* CONFIG_MTD_NOR_FLASH */
 298 }
 299
 300 int board_early_init_f(void)
 301 {
 302         /* TMU0 */
 303         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 304         /* QSPI */
 305         mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
 306
 307         return 0;
 308 }
 309
 310 int board_init(void)
 311 {
 312         /* adress of boot parameters */
 313         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 314
 315         return 0;
 316 }
 317
 318 /* Added for BLANCHE(R-CarV2H board) */
 319 #ifndef CONFIG_DM_ETH
 320 int board_eth_init(bd_t *bis)
 321 {
 322         int rc = 0;
 323
 324 #ifdef CONFIG_SMC911X
 325         struct eth_device *dev;
 326         uchar eth_addr[6];
 327
 328         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 329
 330         if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
 331                 dev = eth_get_dev_by_index(0);
 332                 if (dev) {
 333                         eth_env_set_enetaddr("ethaddr", dev->enetaddr);
 334                 } else {
 335                         printf("blanche: Couldn't get eth device\n");
 336                         rc = -1;
 337                 }
 338         }
 339
 340 #endif
 341
 342         return rc;
 343 }
 344 #endif
 345
 346 int dram_init(void)
 347 {
 348         if (fdtdec_setup_mem_size_base() != 0)
 349                 return -EINVAL;
 350
 351         return 0;
 352 }
 353
 354 int dram_init_banksize(void)
 355 {
 356         fdtdec_setup_memory_banksize();
 357
 358         return 0;
 359 }
 360
 361 void reset_cpu(ulong addr)
 362 {
 363         struct udevice *dev;
 364         const u8 pmic_bus = 6;
 365         const u8 pmic_addr = 0x58;
 366         u8 data;
 367         int ret;
 368
 369         ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
 370         if (ret)
 371                 hang();
 372
 373         ret = dm_i2c_read(dev, 0x13, &data, 1);
 374         if (ret)
 375                 hang();
 376
 377         data |= BIT(1);
 378
 379         ret = dm_i2c_write(dev, 0x13, &data, 1);
 380         if (ret)
 381                 hang();
 382 }