1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com>
8 #include <asm/addrspace.h>
10 #include <mach/ar71xx_regs.h>
12 #include <mach/ath79.h>
13 #include <debug_uart.h>
15 #define RST_RESET_RTC_RESET_LSB 27
16 #define RST_RESET_RTC_RESET_MASK 0x08000000
17 #define RST_RESET_RTC_RESET_SET(x) \
18 (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
20 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
21 void board_debug_uart_init(void)
26 regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
29 /* UART : RX18, TX22 done
30 * GPIO18 as input, GPIO22 as output
32 val = readl(regs + AR71XX_GPIO_REG_OE);
33 val |= QCA956X_GPIO(18);
34 val &= ~QCA956X_GPIO(22);
35 writel(val, regs + AR71XX_GPIO_REG_OE);
38 * Enable GPIO22 as UART0_SOUT
40 val = readl(regs + QCA956X_GPIO_REG_OUT_FUNC5);
41 val &= ~QCA956X_GPIO_MUX_MASK(16);
42 val |= QCA956X_GPIO_OUT_MUX_UART0_SOUT << 16;
43 writel(val, regs + QCA956X_GPIO_REG_OUT_FUNC5);
46 * Enable GPIO18 as UART0_SIN
48 val = readl(regs + QCA956X_GPIO_REG_IN_ENABLE0);
49 val &= ~QCA956X_GPIO_MUX_MASK(8);
50 val |= QCA956X_GPIO_IN_MUX_UART0_SIN << 8;
51 writel(val, regs + QCA956X_GPIO_REG_IN_ENABLE0);
54 * Enable GPIO22 output
56 val = readl(regs + AR71XX_GPIO_REG_OUT);
57 val |= QCA956X_GPIO(22);
58 writel(val, regs + AR71XX_GPIO_REG_OUT);
62 int board_early_init_f(void)
65 void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE,
66 AR71XX_RESET_SIZE, MAP_NOCACHE);
68 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
69 /* CPU:775, DDR:650, AHB:258 */
74 /* Take WMAC out of reset */
75 reg = readl(rst_regs + QCA956X_RESET_REG_RESET_MODULE);
76 reg &= (~RST_RESET_RTC_RESET_SET(1));
77 writel(reg, rst_regs + QCA956X_RESET_REG_RESET_MODULE);