board/purism/librem5/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  * Copyright 2021 Purism
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <errno.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/ddr.h>
  12 #include <asm/arch/imx8mq_pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/mach-imx/boot_mode.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/gpio.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <fsl_esdhc_imx.h>
  20 #include <mmc.h>
  21 #include <power/pmic.h>
  22 #include <power/bd71837.h>
  23 #include <hang.h>
  24 #include <init.h>
  25 #include <spl.h>
  26 #include <usb.h>
  27 #include <dwc3-uboot.h>
  28 #include <linux/delay.h>
  29 #include "librem5.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 void spl_dram_init(void)
  34 {
  35         /* ddr init */
  36         if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
  37                 ddr_init(&dram_timing);
  38         else
  39                 ddr_init(&dram_timing_b0);
  40 }
  41
  42 int spl_board_boot_device(enum boot_device boot_dev_spl)
  43 {
  44         log_debug("%s : starting\n", __func__);
  45
  46         switch (boot_dev_spl) {
  47         case SD1_BOOT:
  48         case MMC1_BOOT:
  49                 return BOOT_DEVICE_MMC1;
  50         case USB_BOOT:
  51                 return BOOT_DEVICE_BOARD;
  52         default:
  53                 return BOOT_DEVICE_NONE;
  54         }
  55 }
  56
  57 #define ECSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
  58
  59 static const iomux_v3_cfg_t ecspi_pads[] = {
  60         IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
  61         IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
  62         IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
  63         IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
  64 };
  65
  66 int board_ecspi_init(void)
  67 {
  68         imx_iomux_v3_setup_multiple_pads(ecspi_pads, ARRAY_SIZE(ecspi_pads));
  69
  70         return 0;
  71 }
  72
  73 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
  74 {
  75         return (bus == 0 && cs == 0) ? (SPI1_SS0) : -1;
  76 }
  77
  78 #define I2C_PAD_CTRL    (PAD_CTL_PUE | PAD_CTL_ODE | PAD_CTL_DSE7 | PAD_CTL_FSEL3)
  79 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  80 struct i2c_pads_info i2c_pad_info1 = {
  81         .scl = {
  82                 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
  83                 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  84                 .gp = IMX_GPIO_NR(5, 14),
  85         },
  86         .sda = {
  87                 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
  88                 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  89                 .gp = IMX_GPIO_NR(5, 15),
  90         },
  91 };
  92
  93 struct i2c_pads_info i2c_pad_info2 = {
  94         .scl = {
  95                 .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | PC,
  96                 .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | PC,
  97                 .gp = IMX_GPIO_NR(5, 16),
  98         },
  99         .sda = {
 100                 .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | PC,
 101                 .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | PC,
 102                 .gp = IMX_GPIO_NR(5, 17),
 103         },
 104 };
 105
 106 struct i2c_pads_info i2c_pad_info3 = {
 107         .scl = {
 108                 .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | PC,
 109                 .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | PC,
 110                 .gp = IMX_GPIO_NR(5, 18),
 111         },
 112         .sda = {
 113                 .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | PC,
 114                 .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | PC,
 115                 .gp = IMX_GPIO_NR(5, 19),
 116         },
 117 };
 118
 119 struct i2c_pads_info i2c_pad_info4 = {
 120         .scl = {
 121                 .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | PC,
 122                 .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | PC,
 123                 .gp = IMX_GPIO_NR(5, 20),
 124         },
 125         .sda = {
 126                 .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | PC,
 127                 .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | PC,
 128                 .gp = IMX_GPIO_NR(5, 21),
 129         },
 130 };
 131
 132 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 133
 134 static const iomux_v3_cfg_t uart_pads[] = {
 135         IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 136         IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 137         IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 138         IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 139         IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 140         IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 141         IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 142         IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 143 };
 144
 145 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
 146 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
 147
 148 int board_mmc_getcd(struct mmc *mmc)
 149 {
 150         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 151         int ret = 0;
 152
 153         switch (cfg->esdhc_base) {
 154         case USDHC1_BASE_ADDR:
 155                 ret = 1;
 156                 break;
 157         case USDHC2_BASE_ADDR:
 158                 ret = 1;
 159                 break;
 160         }
 161
 162         return ret;
 163 }
 164
 165 #define USDHC_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
 166                          PAD_CTL_FSEL1)
 167 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
 168
 169 static const iomux_v3_cfg_t usdhc1_pads[] = {
 170         IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171         IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 172         IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 173         IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 174         IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 175         IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 176         IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 177         IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 178         IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 179         IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 180         IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 181 };
 182
 183 static const iomux_v3_cfg_t usdhc2_pads[] = {
 184         IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 185         IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 186         IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 187         IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 188         IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
 189         IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 190         IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
 191 };
 192
 193 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 194         {USDHC1_BASE_ADDR, 0, 8},
 195         {USDHC2_BASE_ADDR, 0, 4},
 196 };
 197
 198 int board_mmc_init(struct bd_info *bis)
 199 {
 200         int i, ret;
 201         /*
 202          * According to the board_mmc_init() the following map is done:
 203          * (U-Boot device node)    (Physical Port)
 204          * mmc0                    USDHC1
 205          * mmc1                    USDHC2
 206          */
 207         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 208                 log_debug("Initializing FSL USDHC port %d\n", i);
 209                 switch (i) {
 210                 case 0:
 211                         init_clk_usdhc(0);
 212                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
 213                         imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 214                                                          ARRAY_SIZE(usdhc1_pads));
 215                         gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
 216                         gpio_direction_output(USDHC1_PWR_GPIO, 0);
 217                         udelay(500);
 218                         gpio_direction_output(USDHC1_PWR_GPIO, 1);
 219                         break;
 220                 case 1:
 221                         init_clk_usdhc(1);
 222                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
 223                         imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
 224                                                          ARRAY_SIZE(usdhc2_pads));
 225                         gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
 226                         gpio_direction_output(USDHC2_PWR_GPIO, 0);
 227                         udelay(500);
 228                         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 229                         break;
 230                 default:
 231                         log_err("Warning: USDHC controller(%d) not supported\n", i + 1);
 232                         return -EINVAL;
 233                 }
 234
 235                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 236                 if (ret)
 237                         return ret;
 238         }
 239
 240         return 0;
 241 }
 242
 243 #define LDO_VOLT_EN                     BIT(6)
 244
 245 /*
 246  * Disable the charger - it will be re-enabled in u-boot
 247  */
 248 void disable_charger_bq25895(void)
 249 {
 250         u8 val;
 251         int timeout = 1000; // ms
 252
 253         /* Set the i2c bus */
 254         i2c_set_bus_num(3);
 255
 256         /* disable ship mode if BATFET_DLY is set */
 257         val = i2c_reg_read(0x6a, 0x09);
 258         log_debug("REG09 0x%x\n", val);
 259         if (val & 0x28) {
 260                 val = val & ~0x28;
 261                 i2c_reg_write(0x6a, 0x09, val);
 262         }
 263
 264         /* disable and trigger DPDM, ICO, HVDCP and MaxCharge */
 265         val = i2c_reg_read(0x6a, 0x02);
 266         log_debug("REG02 0x%x\n", val);
 267         val &= 0xe0;
 268         i2c_reg_write(0x6a, 0x02, val);
 269
 270         /* disable charger and enable BAT_LOADEN */
 271         val = i2c_reg_read(0x6a, 0x03);
 272         log_debug("REG03 0x%x\n", val);
 273         val = (val | 0x80) & ~0x10;
 274         i2c_reg_write(0x6a, 0x03, val);
 275
 276         mdelay(10);
 277
 278         /* force ADC conversions */
 279         val = i2c_reg_read(0x6a, 0x02);
 280         log_debug("REG02 0x%x\n", val);
 281         val = (val | 0x80) & ~0x40;
 282         i2c_reg_write(0x6a, 0x02, val);
 283
 284         do {
 285                 mdelay(10);
 286                 timeout -= 10;
 287         } while ((i2c_reg_read(0x6a, 0x02) & 0x80) && (timeout > 0));
 288
 289         /* enable STAT pin */
 290         val = i2c_reg_read(0x6a, 0x07);
 291         log_debug("REG07 0x%x\n", val);
 292         val = val & ~0x40;
 293         i2c_reg_write(0x6a, 0x07, val);
 294
 295         /* check VBUS */
 296         val = i2c_reg_read(0x6a, 0x11);
 297         log_debug("VBUS good %d\n", (val >> 7) & 1);
 298         log_debug("VBUS mV %d\n", (val & 0x7f) * 100 + 2600);
 299
 300         /* check VBAT */
 301         val = i2c_reg_read(0x6a, 0x0e);
 302         log_debug("VBAT mV %d\n", (val & 0x7f) * 20 + 2304);
 303
 304         /* limit the VINDPM to 3.9V  */
 305         i2c_reg_write(0x6a, 0x0d, 0x8d);
 306
 307         /* set the max voltage to 4.192V */
 308         val = i2c_reg_read(0x6a, 0x6);
 309         val = (val & ~0xFC) | 0x16 << 2;
 310         i2c_reg_write(0x6a, 0x6, val);
 311
 312         /* set the SYS_MIN to 3.7V */
 313         val = i2c_reg_read(0x6a, 0x3);
 314         val = val | 0xE;
 315         i2c_reg_write(0x6a, 0x3, val);
 316
 317         /* disable BAT_LOADEN */
 318         val = i2c_reg_read(0x6a, 0x03);
 319         log_debug("REG03 0x%x\n", val);
 320         val = val & ~0x80;
 321         i2c_reg_write(0x6a, 0x03, val);
 322 }
 323
 324 #define I2C_PMIC        0
 325
 326 int power_bd71837_init(unsigned char bus)
 327 {
 328         static const char name[] = BD718XX_REGULATOR_DRIVER;
 329         struct pmic *p = pmic_alloc();
 330
 331         if (!p) {
 332                 log_err("%s: POWER allocation error!\n", __func__);
 333                 return -ENOMEM;
 334         }
 335
 336         p->name = name;
 337         p->interface = I2C_PMIC;
 338         p->number_of_regs = BD718XX_MAX_REGISTER;
 339         p->hw.i2c.addr = CONFIG_POWER_BD71837_I2C_ADDR;
 340         p->hw.i2c.tx_num = 1;
 341         p->bus = bus;
 342
 343         return 0;
 344 }
 345
 346 int power_init_board(void)
 347 {
 348         struct pmic *p;
 349         int ldo[] = {BD718XX_LDO5_VOLT, BD718XX_LDO6_VOLT,
 350                      BD71837_LDO7_VOLT};
 351         u32 val;
 352         int i, rv;
 353
 354         /* Set the i2c bus */
 355         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 356
 357         /*
 358          * Init PMIC
 359          */
 360         rv = power_bd71837_init(CONFIG_POWER_BD71837_I2C_BUS);
 361         if (rv) {
 362                 log_err("%s: power_bd71837_init(%d) error %d\n", __func__,
 363                         CONFIG_POWER_BD71837_I2C_BUS, rv);
 364                 goto out;
 365         }
 366
 367         p = pmic_get(BD718XX_REGULATOR_DRIVER);
 368         if (!p) {
 369                 log_err("%s: pmic_get(%s) failed\n", __func__, BD718XX_REGULATOR_DRIVER);
 370                 rv = -ENODEV;
 371                 goto out;
 372         }
 373
 374         rv = pmic_probe(p);
 375         if (rv) {
 376                 log_err("%s: pmic_probe() error %d\n", __func__, rv);
 377                 goto out;
 378         }
 379
 380         /*
 381          * Unlock all regs
 382          */
 383         pmic_reg_write(p, BD718XX_REGLOCK, 0);
 384
 385         /* find the reset cause */
 386         pmic_reg_read(p, 0x29, &val);
 387         log_debug("%s: reset cause %d\n", __func__, val);
 388
 389         /*
 390          * Reconfigure default voltages and disable:
 391          * - BUCK3: VDD_GPU_0V9 (1.00 -> 0.90)
 392          * - BUCK4: VDD_VPU_0V9 (1.00 -> 0.90)
 393          */
 394         pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14);
 395         pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14);
 396
 397         /*
 398          * Enable PHYs voltages: LDO5-7
 399          */
 400         for (i = 0; i < ARRAY_SIZE(ldo); i++) {
 401                 rv = pmic_reg_read(p, ldo[i], &val);
 402                 if (rv) {
 403                         log_err("%s: pmic_read(%x) error %d\n", __func__,
 404                                 ldo[i], rv);
 405                         continue;
 406                 }
 407
 408                 pmic_reg_write(p, ldo[i], val | LDO_VOLT_EN);
 409         }
 410
 411         udelay(500);
 412
 413         rv = 0;
 414 out:
 415         return rv;
 416 }
 417
 418 int usb_gadget_handle_interrupts(void)
 419 {
 420         dwc3_uboot_handle_interrupt(0);
 421         return 0;
 422 }
 423
 424 static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
 425 {
 426         u32 RegData;
 427
 428         RegData = readl(dwc3->base + USB_PHY_CTRL1);
 429         RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
 430                         USB_PHY_CTRL1_COMMONONN);
 431         RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
 432         writel(RegData, dwc3->base + USB_PHY_CTRL1);
 433
 434         RegData = readl(dwc3->base + USB_PHY_CTRL0);
 435         RegData |= USB_PHY_CTRL0_REF_SSP_EN;
 436         RegData &= ~USB_PHY_CTRL0_SSC_RANGE_MASK;
 437         RegData |= USB_PHY_CTRL0_SSC_RANGE_4003PPM;
 438         writel(RegData, dwc3->base + USB_PHY_CTRL0);
 439
 440         RegData = readl(dwc3->base + USB_PHY_CTRL2);
 441         RegData |= USB_PHY_CTRL2_TXENABLEN0;
 442         writel(RegData, dwc3->base + USB_PHY_CTRL2);
 443
 444         RegData = readl(dwc3->base + USB_PHY_CTRL1);
 445         RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
 446         writel(RegData, dwc3->base + USB_PHY_CTRL1);
 447
 448         /* Disable rx term override */
 449         RegData = readl(dwc3->base + USB_PHY_CTRL6);
 450         RegData &= ~USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL;
 451         writel(RegData, dwc3->base + USB_PHY_CTRL6);
 452 }
 453
 454 static struct dwc3_device dwc3_device0_data = {
 455         .maximum_speed = USB_SPEED_HIGH,
 456         .base = USB1_BASE_ADDR,
 457         .dr_mode = USB_DR_MODE_PERIPHERAL,
 458         .index = 0,
 459 };
 460
 461 static struct dwc3_device dwc3_device1_data = {
 462         .maximum_speed = USB_SPEED_HIGH,
 463         .base = USB2_BASE_ADDR,
 464         .dr_mode = USB_DR_MODE_HOST,
 465         .index = 1,
 466 };
 467
 468 int board_usb_init(int index, enum usb_init_type init)
 469 {
 470         int ret = 0;
 471
 472         printf("%s : index %d type %d\n", __func__, index, init);
 473
 474         if (index == 0 && init == USB_INIT_DEVICE) {
 475                 dwc3_nxp_usb_phy_init(&dwc3_device0_data);
 476                 ret = dwc3_uboot_init(&dwc3_device0_data);
 477         }
 478         if (index == 1 && init == USB_INIT_HOST) {
 479                 dwc3_nxp_usb_phy_init(&dwc3_device1_data);
 480                 ret = dwc3_uboot_init(&dwc3_device1_data);
 481         }
 482
 483         return ret;
 484 }
 485
 486 int board_usb_cleanup(int index, enum usb_init_type init)
 487 {
 488         u32 RegData;
 489         struct dwc3_device *dwc3;
 490
 491         printf("%s : %d\n", __func__, index);
 492
 493         if (index == 0 && init == USB_INIT_DEVICE)
 494                 dwc3 = &dwc3_device0_data;
 495         if (index == 1 && init == USB_INIT_HOST)
 496                 dwc3 = &dwc3_device1_data;
 497
 498         dwc3_uboot_exit(index);
 499
 500         /* reset the phy */
 501         RegData = readl(dwc3->base + USB_PHY_CTRL1);
 502         RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
 503                         USB_PHY_CTRL1_COMMONONN);
 504         RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
 505         writel(RegData, dwc3->base + USB_PHY_CTRL1);
 506
 507         /* enable rx term override */
 508         RegData = readl(dwc3->base + USB_PHY_CTRL6);
 509         RegData |= USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL;
 510         writel(RegData, dwc3->base + USB_PHY_CTRL6);
 511
 512         return 0;
 513 }
 514
 515 void spl_board_init(void)
 516 {
 517         if (is_usb_boot())
 518                 puts("USB Boot\n");
 519         else
 520                 puts("Normal Boot\n");
 521 }
 522
 523 void board_boot_order(u32 *spl_boot_list)
 524 {
 525         if (is_usb_boot())
 526                 spl_boot_list[0] = BOOT_DEVICE_BOARD;
 527         else
 528                 spl_boot_list[0] = BOOT_DEVICE_MMC1;
 529 }
 530
 531 #define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
 532
 533 static const iomux_v3_cfg_t wdog_pads[] = {
 534         IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 535 };
 536
 537 void board_init_f(ulong dummy)
 538 {
 539         int ret;
 540         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 541
 542         arch_cpu_init();
 543
 544         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 545         set_wdog_reset(wdog);
 546
 547         init_uart_clk(CONSOLE_UART_CLK);
 548         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 549
 550 #ifdef CONSOLE_ON_UART4
 551         gpio_request(WIFI_EN, "WIFI_EN");
 552         gpio_direction_output(WIFI_EN, 1);
 553 #endif
 554
 555         board_early_init_f();
 556
 557         timer_init();
 558
 559         preloader_console_init();
 560
 561         ret = spl_init();
 562         if (ret) {
 563                 log_err("spl_init() failed: %d\n", ret);
 564                 hang();
 565         }
 566
 567         enable_tzc380();
 568
 569         printf("Initializing pinmux\n");
 570         init_pinmux();
 571         gpio_direction_output(LED_G, 1);
 572         gpio_direction_output(MOTO, 1);
 573         mdelay(50);
 574         gpio_direction_output(MOTO, 0);
 575
 576         /* Enable and configure i2c buses not used below */
 577         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 578         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 579         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
 580
 581         power_init_board();
 582
 583         disable_charger_bq25895();
 584
 585         /* initialize this for M4 even if u-boot doesn't have SF_CMD */
 586         printf("Initializing ECSPI\n");
 587         board_ecspi_init();
 588
 589         /* DDR initialization */
 590         printf("Initializing DRAM\n");
 591         spl_dram_init();
 592 }