1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2021 Purism
11 #include <asm/arch/ddr.h>
12 #include <asm/arch/imx8mq_pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/clock.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/gpio.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <fsl_esdhc_imx.h>
21 #include <power/pmic.h>
22 #include <power/bd71837.h>
27 #include <dwc3-uboot.h>
28 #include <linux/delay.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 void spl_dram_init(void)
36 if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
37 ddr_init(&dram_timing);
39 ddr_init(&dram_timing_b0);
42 int spl_board_boot_device(enum boot_device boot_dev_spl)
44 log_debug("%s : starting\n", __func__);
46 switch (boot_dev_spl) {
49 return BOOT_DEVICE_MMC1;
51 return BOOT_DEVICE_BOARD;
53 return BOOT_DEVICE_NONE;
57 #define ECSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
59 static const iomux_v3_cfg_t ecspi_pads[] = {
60 IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
61 IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
62 IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
63 IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
66 int board_ecspi_init(void)
68 imx_iomux_v3_setup_multiple_pads(ecspi_pads, ARRAY_SIZE(ecspi_pads));
73 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
75 return (bus == 0 && cs == 0) ? (SPI1_SS0) : -1;
78 #define I2C_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_ODE | PAD_CTL_DSE7 | PAD_CTL_FSEL3)
79 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
80 struct i2c_pads_info i2c_pad_info1 = {
82 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
83 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
84 .gp = IMX_GPIO_NR(5, 14),
87 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
88 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
89 .gp = IMX_GPIO_NR(5, 15),
93 struct i2c_pads_info i2c_pad_info2 = {
95 .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | PC,
96 .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | PC,
97 .gp = IMX_GPIO_NR(5, 16),
100 .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | PC,
101 .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | PC,
102 .gp = IMX_GPIO_NR(5, 17),
106 struct i2c_pads_info i2c_pad_info3 = {
108 .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | PC,
109 .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | PC,
110 .gp = IMX_GPIO_NR(5, 18),
113 .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | PC,
114 .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | PC,
115 .gp = IMX_GPIO_NR(5, 19),
119 struct i2c_pads_info i2c_pad_info4 = {
121 .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | PC,
122 .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | PC,
123 .gp = IMX_GPIO_NR(5, 20),
126 .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | PC,
127 .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | PC,
128 .gp = IMX_GPIO_NR(5, 21),
132 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
134 static const iomux_v3_cfg_t uart_pads[] = {
135 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
136 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
137 IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
138 IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
139 IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
140 IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
141 IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
142 IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
145 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
146 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
148 int board_mmc_getcd(struct mmc *mmc)
150 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
153 switch (cfg->esdhc_base) {
154 case USDHC1_BASE_ADDR:
157 case USDHC2_BASE_ADDR:
165 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
167 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
169 static const iomux_v3_cfg_t usdhc1_pads[] = {
170 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
171 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
175 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
180 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
183 static const iomux_v3_cfg_t usdhc2_pads[] = {
184 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
185 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
186 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
187 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
188 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
189 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
190 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
193 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
194 {USDHC1_BASE_ADDR, 0, 8},
195 {USDHC2_BASE_ADDR, 0, 4},
198 int board_mmc_init(struct bd_info *bis)
202 * According to the board_mmc_init() the following map is done:
203 * (U-Boot device node) (Physical Port)
207 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
208 log_debug("Initializing FSL USDHC port %d\n", i);
212 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
213 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
214 ARRAY_SIZE(usdhc1_pads));
215 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
216 gpio_direction_output(USDHC1_PWR_GPIO, 0);
218 gpio_direction_output(USDHC1_PWR_GPIO, 1);
222 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
223 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
224 ARRAY_SIZE(usdhc2_pads));
225 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
226 gpio_direction_output(USDHC2_PWR_GPIO, 0);
228 gpio_direction_output(USDHC2_PWR_GPIO, 1);
231 log_err("Warning: USDHC controller(%d) not supported\n", i + 1);
235 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
243 #define LDO_VOLT_EN BIT(6)
246 * Disable the charger - it will be re-enabled in u-boot
248 void disable_charger_bq25895(void)
251 int timeout = 1000; // ms
253 /* Set the i2c bus */
256 /* disable ship mode if BATFET_DLY is set */
257 val = i2c_reg_read(0x6a, 0x09);
258 log_debug("REG09 0x%x\n", val);
261 i2c_reg_write(0x6a, 0x09, val);
264 /* disable and trigger DPDM, ICO, HVDCP and MaxCharge */
265 val = i2c_reg_read(0x6a, 0x02);
266 log_debug("REG02 0x%x\n", val);
268 i2c_reg_write(0x6a, 0x02, val);
270 /* disable charger and enable BAT_LOADEN */
271 val = i2c_reg_read(0x6a, 0x03);
272 log_debug("REG03 0x%x\n", val);
273 val = (val | 0x80) & ~0x10;
274 i2c_reg_write(0x6a, 0x03, val);
278 /* force ADC conversions */
279 val = i2c_reg_read(0x6a, 0x02);
280 log_debug("REG02 0x%x\n", val);
281 val = (val | 0x80) & ~0x40;
282 i2c_reg_write(0x6a, 0x02, val);
287 } while ((i2c_reg_read(0x6a, 0x02) & 0x80) && (timeout > 0));
289 /* enable STAT pin */
290 val = i2c_reg_read(0x6a, 0x07);
291 log_debug("REG07 0x%x\n", val);
293 i2c_reg_write(0x6a, 0x07, val);
296 val = i2c_reg_read(0x6a, 0x11);
297 log_debug("VBUS good %d\n", (val >> 7) & 1);
298 log_debug("VBUS mV %d\n", (val & 0x7f) * 100 + 2600);
301 val = i2c_reg_read(0x6a, 0x0e);
302 log_debug("VBAT mV %d\n", (val & 0x7f) * 20 + 2304);
304 /* limit the VINDPM to 3.9V */
305 i2c_reg_write(0x6a, 0x0d, 0x8d);
307 /* set the max voltage to 4.192V */
308 val = i2c_reg_read(0x6a, 0x6);
309 val = (val & ~0xFC) | 0x16 << 2;
310 i2c_reg_write(0x6a, 0x6, val);
312 /* set the SYS_MIN to 3.7V */
313 val = i2c_reg_read(0x6a, 0x3);
315 i2c_reg_write(0x6a, 0x3, val);
317 /* disable BAT_LOADEN */
318 val = i2c_reg_read(0x6a, 0x03);
319 log_debug("REG03 0x%x\n", val);
321 i2c_reg_write(0x6a, 0x03, val);
326 int power_bd71837_init(unsigned char bus)
328 static const char name[] = BD718XX_REGULATOR_DRIVER;
329 struct pmic *p = pmic_alloc();
332 log_err("%s: POWER allocation error!\n", __func__);
337 p->interface = I2C_PMIC;
338 p->number_of_regs = BD718XX_MAX_REGISTER;
339 p->hw.i2c.addr = CONFIG_POWER_BD71837_I2C_ADDR;
340 p->hw.i2c.tx_num = 1;
346 int power_init_board(void)
349 int ldo[] = {BD718XX_LDO5_VOLT, BD718XX_LDO6_VOLT,
354 /* Set the i2c bus */
355 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
360 rv = power_bd71837_init(CONFIG_POWER_BD71837_I2C_BUS);
362 log_err("%s: power_bd71837_init(%d) error %d\n", __func__,
363 CONFIG_POWER_BD71837_I2C_BUS, rv);
367 p = pmic_get(BD718XX_REGULATOR_DRIVER);
369 log_err("%s: pmic_get(%s) failed\n", __func__, BD718XX_REGULATOR_DRIVER);
376 log_err("%s: pmic_probe() error %d\n", __func__, rv);
383 pmic_reg_write(p, BD718XX_REGLOCK, 0);
385 /* find the reset cause */
386 pmic_reg_read(p, 0x29, &val);
387 log_debug("%s: reset cause %d\n", __func__, val);
390 * Reconfigure default voltages and disable:
391 * - BUCK3: VDD_GPU_0V9 (1.00 -> 0.90)
392 * - BUCK4: VDD_VPU_0V9 (1.00 -> 0.90)
394 pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14);
395 pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14);
398 * Enable PHYs voltages: LDO5-7
400 for (i = 0; i < ARRAY_SIZE(ldo); i++) {
401 rv = pmic_reg_read(p, ldo[i], &val);
403 log_err("%s: pmic_read(%x) error %d\n", __func__,
408 pmic_reg_write(p, ldo[i], val | LDO_VOLT_EN);
418 int usb_gadget_handle_interrupts(void)
420 dwc3_uboot_handle_interrupt(0);
424 static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
428 RegData = readl(dwc3->base + USB_PHY_CTRL1);
429 RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
430 USB_PHY_CTRL1_COMMONONN);
431 RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
432 writel(RegData, dwc3->base + USB_PHY_CTRL1);
434 RegData = readl(dwc3->base + USB_PHY_CTRL0);
435 RegData |= USB_PHY_CTRL0_REF_SSP_EN;
436 RegData &= ~USB_PHY_CTRL0_SSC_RANGE_MASK;
437 RegData |= USB_PHY_CTRL0_SSC_RANGE_4003PPM;
438 writel(RegData, dwc3->base + USB_PHY_CTRL0);
440 RegData = readl(dwc3->base + USB_PHY_CTRL2);
441 RegData |= USB_PHY_CTRL2_TXENABLEN0;
442 writel(RegData, dwc3->base + USB_PHY_CTRL2);
444 RegData = readl(dwc3->base + USB_PHY_CTRL1);
445 RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
446 writel(RegData, dwc3->base + USB_PHY_CTRL1);
448 /* Disable rx term override */
449 RegData = readl(dwc3->base + USB_PHY_CTRL6);
450 RegData &= ~USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL;
451 writel(RegData, dwc3->base + USB_PHY_CTRL6);
454 static struct dwc3_device dwc3_device0_data = {
455 .maximum_speed = USB_SPEED_HIGH,
456 .base = USB1_BASE_ADDR,
457 .dr_mode = USB_DR_MODE_PERIPHERAL,
461 static struct dwc3_device dwc3_device1_data = {
462 .maximum_speed = USB_SPEED_HIGH,
463 .base = USB2_BASE_ADDR,
464 .dr_mode = USB_DR_MODE_HOST,
468 int board_usb_init(int index, enum usb_init_type init)
472 printf("%s : index %d type %d\n", __func__, index, init);
474 if (index == 0 && init == USB_INIT_DEVICE) {
475 dwc3_nxp_usb_phy_init(&dwc3_device0_data);
476 ret = dwc3_uboot_init(&dwc3_device0_data);
478 if (index == 1 && init == USB_INIT_HOST) {
479 dwc3_nxp_usb_phy_init(&dwc3_device1_data);
480 ret = dwc3_uboot_init(&dwc3_device1_data);
486 int board_usb_cleanup(int index, enum usb_init_type init)
489 struct dwc3_device *dwc3;
491 printf("%s : %d\n", __func__, index);
493 if (index == 0 && init == USB_INIT_DEVICE)
494 dwc3 = &dwc3_device0_data;
495 if (index == 1 && init == USB_INIT_HOST)
496 dwc3 = &dwc3_device1_data;
498 dwc3_uboot_exit(index);
501 RegData = readl(dwc3->base + USB_PHY_CTRL1);
502 RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
503 USB_PHY_CTRL1_COMMONONN);
504 RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
505 writel(RegData, dwc3->base + USB_PHY_CTRL1);
507 /* enable rx term override */
508 RegData = readl(dwc3->base + USB_PHY_CTRL6);
509 RegData |= USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL;
510 writel(RegData, dwc3->base + USB_PHY_CTRL6);
515 void spl_board_init(void)
520 puts("Normal Boot\n");
523 void board_boot_order(u32 *spl_boot_list)
526 spl_boot_list[0] = BOOT_DEVICE_BOARD;
528 spl_boot_list[0] = BOOT_DEVICE_MMC1;
531 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
533 static const iomux_v3_cfg_t wdog_pads[] = {
534 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
537 void board_init_f(ulong dummy)
540 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
544 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
545 set_wdog_reset(wdog);
547 init_uart_clk(CONSOLE_UART_CLK);
548 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
550 #ifdef CONSOLE_ON_UART4
551 gpio_request(WIFI_EN, "WIFI_EN");
552 gpio_direction_output(WIFI_EN, 1);
555 board_early_init_f();
559 preloader_console_init();
563 log_err("spl_init() failed: %d\n", ret);
569 printf("Initializing pinmux\n");
571 gpio_direction_output(LED_G, 1);
572 gpio_direction_output(MOTO, 1);
574 gpio_direction_output(MOTO, 0);
576 /* Enable and configure i2c buses not used below */
577 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
578 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
579 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
583 disable_charger_bq25895();
585 /* initialize this for M4 even if u-boot doesn't have SF_CMD */
586 printf("Initializing ECSPI\n");
589 /* DDR initialization */
590 printf("Initializing DRAM\n");