1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux-mx28.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <linux/delay.h>
18 #include <linux/mii.h>
23 DECLARE_GLOBAL_DATA_PTR;
28 int board_early_init_f(void)
30 /* IO0 clock at 480MHz */
31 mxs_set_ioclk(MXC_IOCLK0, 480000);
32 /* IO1 clock at 480MHz */
33 mxs_set_ioclk(MXC_IOCLK1, 480000);
35 /* SSP2 clock at 160MHz */
36 mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
43 return mxs_dram_init();
48 /* Adress of boot parameters */
49 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
55 int board_eth_init(bd_t *bis)
57 struct mxs_clkctrl_regs *clkctrl_regs =
58 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
59 struct eth_device *dev;
62 ret = cpu_eth_init(bis);
64 /* BG0900 uses ENET_CLK PAD to drive FEC clock */
65 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
66 &clkctrl_regs->hw_clkctrl_enet);
69 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
71 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
73 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
75 puts("FEC MXS: Unable to init FEC0\n");
79 dev = eth_get_dev_by_name("FEC0");
81 puts("FEC MXS: Unable to get FEC0 device entry\n");