board/phytium/durian/durian.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * shuyiqi <shuyiqi@phytium.com.cn>
   5  * liuhao  <liuhao@phytium.com.cn>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/armv8/mmu.h>
  11 #include <asm/cache.h>
  12 #include <asm/system.h>
  13 #include <asm/io.h>
  14 #include <linux/arm-smccc.h>
  15 #include <linux/kernel.h>
  16 #include <scsi.h>
  17 #include "cpu.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 int dram_init(void)
  22 {
  23         gd->mem_clk = 0;
  24         gd->ram_size = PHYS_SDRAM_1_SIZE;
  25         return 0;
  26 }
  27
  28 int dram_init_banksize(void)
  29 {
  30         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  31         gd->bd->bi_dram[0].size =  PHYS_SDRAM_1_SIZE;
  32
  33         return 0;
  34 }
  35
  36 int board_init(void)
  37 {
  38         return 0;
  39 }
  40
  41 void reset_cpu(ulong addr)
  42 {
  43         struct arm_smccc_res res;
  44
  45         arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
  46         debug("reset cpu error, %lx\n", res.a0);
  47 }
  48
  49 static struct mm_region durian_mem_map[] = {
  50         {
  51                 .virt = 0x0UL,
  52                 .phys = 0x0UL,
  53                 .size = 0x80000000UL,
  54                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  55                                  PTE_BLOCK_NON_SHARE |
  56                                  PTE_BLOCK_PXN |
  57                                  PTE_BLOCK_UXN
  58         },
  59         {
  60                 .virt = (u64)PHYS_SDRAM_1,
  61                 .phys = (u64)PHYS_SDRAM_1,
  62                 .size = (u64)PHYS_SDRAM_1_SIZE,
  63                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  64                                  PTE_BLOCK_NS |
  65                                  PTE_BLOCK_INNER_SHARE
  66         },
  67         {
  68                 0,
  69         }
  70 };
  71
  72 struct mm_region *mem_map = durian_mem_map;
  73
  74 int print_cpuinfo(void)
  75 {
  76         printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
  77         return 0;
  78 }
  79
  80 int __asm_flush_l3_dcache(void)
  81 {
  82         int i, pstate;
  83
  84         for (i = 0; i < HNF_COUNT; i++)
  85                 writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
  86         for (i = 0; i < HNF_COUNT; i++) {
  87                 do {
  88                         pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
  89                 } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
  90         }
  91
  92         for (i = 0; i < HNF_COUNT; i++)
  93                 writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
  94
  95         return 0;
  96 }
  97
  98 int last_stage_init(void)
  99 {
 100         int ret;
 101
 102         /* pci e */
 103         pci_init();
 104         /* scsi scan */
 105         ret = scsi_scan(true);
 106         if (ret) {
 107                 printf("scsi scan failed\n");
 108                 return CMD_RET_FAILURE;
 109         }
 110         return ret;
 111 }
 112