board/phytec/phycore_imx8mm/spl.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
   4  * Author: Teresa Remmet <t.remmet@phytec.de>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/ddr.h>
  10 #include <asm/arch/imx8mm_pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/mach-imx/boot_mode.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <dm/device.h>
  15 #include <dm/uclass.h>
  16 #include <hang.h>
  17 #include <init.h>
  18 #include <log.h>
  19 #include <spl.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 int spl_board_boot_device(enum boot_device boot_dev_spl)
  24 {
  25         switch (boot_dev_spl) {
  26         case SD2_BOOT:
  27         case MMC2_BOOT:
  28                 return BOOT_DEVICE_MMC1;
  29         case SD3_BOOT:
  30         case MMC3_BOOT:
  31                 return BOOT_DEVICE_MMC2;
  32         case QSPI_BOOT:
  33                 return BOOT_DEVICE_NOR;
  34         case USB_BOOT:
  35                 return BOOT_DEVICE_BOARD;
  36         default:
  37                 return BOOT_DEVICE_NONE;
  38         }
  39 }
  40
  41 void spl_dram_init(void)
  42 {
  43         ddr_init(&dram_timing);
  44 }
  45
  46 void spl_board_init(void)
  47 {
  48         /* Serial download mode */
  49         if (is_usb_boot()) {
  50                 puts("Back to ROM, SDP\n");
  51                 restore_boot_params();
  52         }
  53         puts("Normal Boot\n");
  54 }
  55
  56 #ifdef CONFIG_SPL_LOAD_FIT
  57 int board_fit_config_name_match(const char *name)
  58 {
  59         /* Just empty function now - can't decide what to choose */
  60         debug("%s: %s\n", __func__, name);
  61
  62         return 0;
  63 }
  64 #endif
  65
  66 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  67 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE)
  68
  69 static iomux_v3_cfg_t const uart_pads[] = {
  70         IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  71         IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  72 };
  73
  74 static iomux_v3_cfg_t const wdog_pads[] = {
  75         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  76 };
  77
  78 int board_early_init_f(void)
  79 {
  80         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  81
  82         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  83
  84         set_wdog_reset(wdog);
  85
  86         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  87
  88         return 0;
  89 }
  90
  91 void board_init_f(ulong dummy)
  92 {
  93         struct udevice *dev;
  94         int ret;
  95
  96         arch_cpu_init();
  97
  98         init_uart_clk(2);
  99
 100         board_early_init_f();
 101
 102         timer_init();
 103
 104         preloader_console_init();
 105
 106         /* Clear the BSS. */
 107         memset(__bss_start, 0, __bss_end - __bss_start);
 108
 109         ret = spl_early_init();
 110         if (ret) {
 111                 debug("spl_early_init() failed: %d\n", ret);
 112                 hang();
 113         }
 114
 115         ret = uclass_get_device_by_name(UCLASS_CLK,
 116                                         "clock-controller@30380000", &dev);
 117         if (ret < 0) {
 118                 printf("Failed to find clock node. Check device tree\n");
 119                 hang();
 120         }
 121
 122         enable_tzc380();
 123
 124         /* DDR initialization */
 125         spl_dram_init();
 126
 127         board_init_r(NULL, 0);
 128 }