board/phytec/phycore_am335x_r2/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
   9  * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
  10  * Copyright (C) 2019 DENX Software Engineering GmbH
  11  */
  12
  13 #include <common.h>
  14 #include <init.h>
  15 #include <spl.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/global_data.h>
  21 #include <power/tps65910.h>
  22 #include <jffs2/load_kernel.h>
  23 #include <mtd_node.h>
  24 #include <fdt_support.h>
  25 #include "board.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_SPL_BUILD
  30
  31 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  32
  33 /* DDR RAM defines */
  34 #define DDR_CLK_MHZ             400 /* DDR_DPLL_MULT value */
  35
  36 #define OSC     (V_OSCK / 1000000)
  37 const struct dpll_params dpll_ddr = {
  38                 DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
  39
  40 const struct dpll_params *get_dpll_ddr_params(void)
  41 {
  42         return &dpll_ddr;
  43 }
  44
  45 const struct ctrl_ioregs ioregs = {
  46         .cm0ioctl               = 0x18B,
  47         .cm1ioctl               = 0x18B,
  48         .cm2ioctl               = 0x18B,
  49         .dt0ioctl               = 0x18B,
  50         .dt1ioctl               = 0x18B,
  51 };
  52
  53 static const struct cmd_control ddr3_cmd_ctrl_data = {
  54         .cmd0csratio = 0x80,
  55         .cmd0iclkout = 0x0,
  56
  57         .cmd1csratio = 0x80,
  58         .cmd1iclkout = 0x0,
  59
  60         .cmd2csratio = 0x80,
  61         .cmd2iclkout = 0x0,
  62 };
  63
  64 enum {
  65         PHYCORE_R2_MT41K128M16JT_256MB,
  66         PHYCORE_R2_MT41K256M16TW107IT_512MB,
  67         PHYCORE_R2_MT41K512M16HA125IT_1024MB,
  68 };
  69
  70 struct am335x_sdram_timings {
  71         struct emif_regs ddr3_emif_reg_data;
  72         struct ddr_data ddr3_data;
  73 };
  74
  75 static struct am335x_sdram_timings physom_timings[] = {
  76         [PHYCORE_R2_MT41K128M16JT_256MB] = {
  77                 .ddr3_emif_reg_data = {
  78                         .sdram_config = 0x61C052B2,
  79                         .ref_ctrl = 0x00000C30,
  80                         .sdram_tim1 = 0x0AAAD4DB,
  81                         .sdram_tim2 = 0x26437FDA,
  82                         .sdram_tim3 = 0x501F83FF,
  83                         .zq_config = 0x50074BE4,
  84                         .emif_ddr_phy_ctlr_1 = 0x7,
  85                         .ocp_config = 0x003d3d3d,
  86                 },
  87                 .ddr3_data = {
  88                         .datardsratio0 = 0x36,
  89                         .datawdsratio0 = 0x38,
  90                         .datafwsratio0 = 0x99,
  91                         .datawrsratio0 = 0x73,
  92                 },
  93         },
  94         [PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
  95                 .ddr3_emif_reg_data = {
  96                         .sdram_config = 0x61C05332,
  97                         .ref_ctrl = 0x00000C30,
  98                         .sdram_tim1 = 0x0AAAD4DB,
  99                         .sdram_tim2 = 0x266B7FDA,
 100                         .sdram_tim3 = 0x501F867F,
 101                         .zq_config = 0x50074BE4,
 102                         .emif_ddr_phy_ctlr_1 = 0x7,
 103                         .ocp_config = 0x003d3d3d,
 104                 },
 105                 .ddr3_data = {
 106                         .datardsratio0 = 0x37,
 107                         .datawdsratio0 = 0x38,
 108                         .datafwsratio0 = 0x92,
 109                         .datawrsratio0 = 0x72,
 110                 },
 111         },
 112         [PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
 113                 .ddr3_emif_reg_data = {
 114                         .sdram_config = 0x61C053B2,
 115                         .ref_ctrl = 0x00000C30,
 116                         .sdram_tim1 = 0x0AAAD4DB,
 117                         .sdram_tim2 = 0x268F7FDA,
 118                         .sdram_tim3 = 0x501F88BF,
 119                         .zq_config = 0x50074BE4,
 120                         .emif_ddr_phy_ctlr_1 = 0x7,
 121                         .ocp_config = 0x003d3d3d,
 122                 },
 123                 .ddr3_data = {
 124                         .datardsratio0 = 0x38,
 125                         .datawdsratio0 = 0x4d,
 126                         .datafwsratio0 = 0x9d,
 127                         .datawrsratio0 = 0x82,
 128                 },
 129         },
 130 };
 131
 132 void sdram_init(void)
 133 {
 134         /* Configure memory to maximum supported size for detection */
 135         int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
 136
 137         config_ddr(DDR_CLK_MHZ, &ioregs,
 138                    &physom_timings[ram_type_index].ddr3_data,
 139                    &ddr3_cmd_ctrl_data,
 140                    &physom_timings[ram_type_index].ddr3_emif_reg_data,
 141                    0);
 142
 143         /* Detect memory physically present */
 144         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 145                                     CONFIG_MAX_RAM_BANK_SIZE);
 146
 147         /* Reconfigure memory for actual detected size */
 148         switch (gd->ram_size) {
 149         case SZ_1G:
 150                 ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
 151                 break;
 152         case SZ_512M:
 153                 ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
 154                 break;
 155         case SZ_256M:
 156         default:
 157                 ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
 158                 break;
 159         }
 160         config_ddr(DDR_CLK_MHZ, &ioregs,
 161                    &physom_timings[ram_type_index].ddr3_data,
 162                    &ddr3_cmd_ctrl_data,
 163                    &physom_timings[ram_type_index].ddr3_emif_reg_data,
 164                    0);
 165 }
 166
 167 const struct dpll_params *get_dpll_mpu_params(void)
 168 {
 169         int ind = get_sys_clk_index();
 170         int freq = am335x_get_efuse_mpu_max_freq(cdev);
 171
 172         switch (freq) {
 173         case MPUPLL_M_1000:
 174                 return &dpll_mpu_opp[ind][5];
 175         case MPUPLL_M_800:
 176                 return &dpll_mpu_opp[ind][4];
 177         case MPUPLL_M_720:
 178                 return &dpll_mpu_opp[ind][3];
 179         case MPUPLL_M_600:
 180                 return &dpll_mpu_opp[ind][2];
 181         case MPUPLL_M_500:
 182                 return &dpll_mpu_opp100;
 183         case MPUPLL_M_300:
 184                 return &dpll_mpu_opp[ind][0];
 185         }
 186
 187         return &dpll_mpu_opp[ind][0];
 188 }
 189
 190 static void scale_vcores_generic(int freq)
 191 {
 192         int sil_rev, mpu_vdd;
 193
 194         /*
 195          * We use a TPS65910 PMIC. For all  MPU frequencies we support we use a
 196          * CORE voltage of 1.10V. For MPU voltage we need to switch based on
 197          * the frequency we are running at.
 198          */
 199         if (power_tps65910_init(0))
 200                 return;
 201
 202         /*
 203          * Depending on MPU clock and PG we will need a different
 204          * VDD to drive at that speed.
 205          */
 206         sil_rev = readl(&cdev->deviceid) >> 28;
 207         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 208
 209         /* Tell the TPS65910 to use i2c */
 210         tps65910_set_i2c_control();
 211
 212         /* First update MPU voltage. */
 213         if (tps65910_voltage_update(MPU, mpu_vdd))
 214                 return;
 215
 216         /* Second, update the CORE voltage. */
 217         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
 218                 return;
 219 }
 220
 221 void scale_vcores(void)
 222 {
 223         int freq;
 224
 225         freq = am335x_get_efuse_mpu_max_freq(cdev);
 226         scale_vcores_generic(freq);
 227 }
 228
 229 void set_uart_mux_conf(void)
 230 {
 231         enable_uart0_pin_mux();
 232 }
 233
 234 void set_mux_conf_regs(void)
 235 {
 236         enable_i2c0_pin_mux();
 237         enable_board_pin_mux();
 238 }
 239 #endif
 240
 241 /*
 242  * Basic board specific setup.  Pinmux has been handled already.
 243  */
 244 int board_init(void)
 245 {
 246         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 247         return 0;
 248 }
 249
 250 #ifdef CONFIG_OF_BOARD_SETUP
 251 int ft_board_setup(void *blob, struct bd_info *bd)
 252 {
 253 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 254         static const struct node_info nodes[] = {
 255                 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
 256         };
 257
 258         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 259 #endif
 260         return 0;
 261 }
 262 #endif