board/phytec/phycore_am335x_r2/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
   9  * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
  10  * Copyright (C) 2019 DENX Software Engineering GmbH
  11  */
  12
  13 #include <common.h>
  14 #include <spl.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/ddr_defs.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <power/tps65910.h>
  20 #include <jffs2/load_kernel.h>
  21 #include <mtd_node.h>
  22 #include <fdt_support.h>
  23 #include "board.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #ifdef CONFIG_SPL_BUILD
  28
  29 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  30
  31 /* DDR RAM defines */
  32 #define DDR_CLK_MHZ             400 /* DDR_DPLL_MULT value */
  33
  34 #define OSC     (V_OSCK / 1000000)
  35 const struct dpll_params dpll_ddr = {
  36                 DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
  37
  38 const struct dpll_params *get_dpll_ddr_params(void)
  39 {
  40         return &dpll_ddr;
  41 }
  42
  43 const struct ctrl_ioregs ioregs = {
  44         .cm0ioctl               = 0x18B,
  45         .cm1ioctl               = 0x18B,
  46         .cm2ioctl               = 0x18B,
  47         .dt0ioctl               = 0x18B,
  48         .dt1ioctl               = 0x18B,
  49 };
  50
  51 static const struct cmd_control ddr3_cmd_ctrl_data = {
  52         .cmd0csratio = 0x80,
  53         .cmd0iclkout = 0x0,
  54
  55         .cmd1csratio = 0x80,
  56         .cmd1iclkout = 0x0,
  57
  58         .cmd2csratio = 0x80,
  59         .cmd2iclkout = 0x0,
  60 };
  61
  62 enum {
  63         PHYCORE_R2_MT41K128M16JT_256MB,
  64         PHYCORE_R2_MT41K256M16TW107IT_512MB,
  65         PHYCORE_R2_MT41K512M16HA125IT_1024MB,
  66 };
  67
  68 struct am335x_sdram_timings {
  69         struct emif_regs ddr3_emif_reg_data;
  70         struct ddr_data ddr3_data;
  71 };
  72
  73 static struct am335x_sdram_timings physom_timings[] = {
  74         [PHYCORE_R2_MT41K128M16JT_256MB] = {
  75                 .ddr3_emif_reg_data = {
  76                         .sdram_config = 0x61C052B2,
  77                         .ref_ctrl = 0x00000C30,
  78                         .sdram_tim1 = 0x0AAAD4DB,
  79                         .sdram_tim2 = 0x26437FDA,
  80                         .sdram_tim3 = 0x501F83FF,
  81                         .zq_config = 0x50074BE4,
  82                         .emif_ddr_phy_ctlr_1 = 0x7,
  83                         .ocp_config = 0x003d3d3d,
  84                 },
  85                 .ddr3_data = {
  86                         .datardsratio0 = 0x36,
  87                         .datawdsratio0 = 0x38,
  88                         .datafwsratio0 = 0x99,
  89                         .datawrsratio0 = 0x73,
  90                 },
  91         },
  92         [PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
  93                 .ddr3_emif_reg_data = {
  94                         .sdram_config = 0x61C05332,
  95                         .ref_ctrl = 0x00000C30,
  96                         .sdram_tim1 = 0x0AAAD4DB,
  97                         .sdram_tim2 = 0x266B7FDA,
  98                         .sdram_tim3 = 0x501F867F,
  99                         .zq_config = 0x50074BE4,
 100                         .emif_ddr_phy_ctlr_1 = 0x7,
 101                         .ocp_config = 0x003d3d3d,
 102                 },
 103                 .ddr3_data = {
 104                         .datardsratio0 = 0x37,
 105                         .datawdsratio0 = 0x38,
 106                         .datafwsratio0 = 0x92,
 107                         .datawrsratio0 = 0x72,
 108                 },
 109         },
 110         [PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
 111                 .ddr3_emif_reg_data = {
 112                         .sdram_config = 0x61C053B2,
 113                         .ref_ctrl = 0x00000C30,
 114                         .sdram_tim1 = 0x0AAAD4DB,
 115                         .sdram_tim2 = 0x268F7FDA,
 116                         .sdram_tim3 = 0x501F88BF,
 117                         .zq_config = 0x50074BE4,
 118                         .emif_ddr_phy_ctlr_1 = 0x7,
 119                         .ocp_config = 0x003d3d3d,
 120                 },
 121                 .ddr3_data = {
 122                         .datardsratio0 = 0x38,
 123                         .datawdsratio0 = 0x4d,
 124                         .datafwsratio0 = 0x9d,
 125                         .datawrsratio0 = 0x82,
 126                 },
 127         },
 128 };
 129
 130 void sdram_init(void)
 131 {
 132         /* Configure memory to maximum supported size for detection */
 133         int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
 134
 135         config_ddr(DDR_CLK_MHZ, &ioregs,
 136                    &physom_timings[ram_type_index].ddr3_data,
 137                    &ddr3_cmd_ctrl_data,
 138                    &physom_timings[ram_type_index].ddr3_emif_reg_data,
 139                    0);
 140
 141         /* Detect memory physically present */
 142         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 143                                     CONFIG_MAX_RAM_BANK_SIZE);
 144
 145         /* Reconfigure memory for actual detected size */
 146         switch (gd->ram_size) {
 147         case SZ_1G:
 148                 ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
 149                 break;
 150         case SZ_512M:
 151                 ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
 152                 break;
 153         case SZ_256M:
 154         default:
 155                 ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
 156                 break;
 157         }
 158         config_ddr(DDR_CLK_MHZ, &ioregs,
 159                    &physom_timings[ram_type_index].ddr3_data,
 160                    &ddr3_cmd_ctrl_data,
 161                    &physom_timings[ram_type_index].ddr3_emif_reg_data,
 162                    0);
 163 }
 164
 165 const struct dpll_params *get_dpll_mpu_params(void)
 166 {
 167         int ind = get_sys_clk_index();
 168         int freq = am335x_get_efuse_mpu_max_freq(cdev);
 169
 170         switch (freq) {
 171         case MPUPLL_M_1000:
 172                 return &dpll_mpu_opp[ind][5];
 173         case MPUPLL_M_800:
 174                 return &dpll_mpu_opp[ind][4];
 175         case MPUPLL_M_720:
 176                 return &dpll_mpu_opp[ind][3];
 177         case MPUPLL_M_600:
 178                 return &dpll_mpu_opp[ind][2];
 179         case MPUPLL_M_500:
 180                 return &dpll_mpu_opp100;
 181         case MPUPLL_M_300:
 182                 return &dpll_mpu_opp[ind][0];
 183         }
 184
 185         return &dpll_mpu_opp[ind][0];
 186 }
 187
 188 static void scale_vcores_generic(int freq)
 189 {
 190         int sil_rev, mpu_vdd;
 191
 192         /*
 193          * We use a TPS65910 PMIC. For all  MPU frequencies we support we use a
 194          * CORE voltage of 1.10V. For MPU voltage we need to switch based on
 195          * the frequency we are running at.
 196          */
 197         if (power_tps65910_init(0))
 198                 return;
 199
 200         /*
 201          * Depending on MPU clock and PG we will need a different
 202          * VDD to drive at that speed.
 203          */
 204         sil_rev = readl(&cdev->deviceid) >> 28;
 205         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 206
 207         /* Tell the TPS65910 to use i2c */
 208         tps65910_set_i2c_control();
 209
 210         /* First update MPU voltage. */
 211         if (tps65910_voltage_update(MPU, mpu_vdd))
 212                 return;
 213
 214         /* Second, update the CORE voltage. */
 215         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
 216                 return;
 217 }
 218
 219 void scale_vcores(void)
 220 {
 221         int freq;
 222
 223         freq = am335x_get_efuse_mpu_max_freq(cdev);
 224         scale_vcores_generic(freq);
 225 }
 226
 227 void set_uart_mux_conf(void)
 228 {
 229         enable_uart0_pin_mux();
 230 }
 231
 232 void set_mux_conf_regs(void)
 233 {
 234         enable_i2c0_pin_mux();
 235         enable_board_pin_mux();
 236 }
 237 #endif
 238
 239 /*
 240  * Basic board specific setup.  Pinmux has been handled already.
 241  */
 242 int board_init(void)
 243 {
 244         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 245         return 0;
 246 }
 247
 248 #ifdef CONFIG_OF_BOARD_SETUP
 249 int ft_board_setup(void *blob, bd_t *bd)
 250 {
 251 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 252         static const struct node_info nodes[] = {
 253                 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
 254         };
 255
 256         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 257 #endif
 258         return 0;
 259 }
 260 #endif