board/phytec/pcm052/pcm052.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
   5  *
   6  * Copyright 2013 Freescale Semiconductor, Inc.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux-vf610.h>
  13 #include <asm/arch/ddrmc-vf610.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/clock.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 static struct ddrmc_cr_setting pcm052_cr_settings[] = {
  20         /* not in the datasheets, but in the original code */
  21         { 0x00002000, 105 },
  22         { 0x00000020, 110 },
  23         /* AXI */
  24         { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
  25         { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  26         { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  27                    DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  28         { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  29                    DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  30         { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  31                    DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  32         { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  33                    DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  34         { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  35         { DDRMC_CR126_PHY_RDLAT(11), 126 },
  36         { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
  37         { DDRMC_CR137_PHYCTL_DL(2), 137 },
  38         { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  39                    DDRMC_CR139_PHY_WRLV_DLL(3) |
  40                    DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  41         { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  42                    DDRMC_CR154_PAD_ZQ_MODE(1) |
  43                    DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  44                    DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
  45         { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
  46         { DDRMC_CR158_TWR(6), 158 },
  47         { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
  48                    DDRMC_CR161_TODTH_WR(6), 161 },
  49         /* end marker */
  50         { 0, -1 }
  51 };
  52
  53 /* PHY settings -- most of them differ from default in imx-regs.h */
  54
  55 #define PCM052_DDRMC_PHY_DQ_TIMING                      0x00002213
  56 #define PCM052_DDRMC_PHY_CTRL                           0x00290000
  57 #define PCM052_DDRMC_PHY_SLAVE_CTRL                     0x00002c00
  58 #define PCM052_DDRMC_PHY_PROC_PAD_ODT                   0x00010020
  59
  60 static struct ddrmc_phy_setting pcm052_phy_settings[] = {
  61         { PCM052_DDRMC_PHY_DQ_TIMING,  0 },
  62         { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
  63         { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
  64         { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
  65         { DDRMC_PHY_DQS_TIMING,  1 },
  66         { DDRMC_PHY_DQS_TIMING, 17 },
  67         { DDRMC_PHY_DQS_TIMING, 33 },
  68         { DDRMC_PHY_DQS_TIMING, 49 },
  69         { PCM052_DDRMC_PHY_CTRL,  2 },
  70         { PCM052_DDRMC_PHY_CTRL, 18 },
  71         { PCM052_DDRMC_PHY_CTRL, 34 },
  72         { DDRMC_PHY_MASTER_CTRL,  3 },
  73         { DDRMC_PHY_MASTER_CTRL, 19 },
  74         { DDRMC_PHY_MASTER_CTRL, 35 },
  75         { PCM052_DDRMC_PHY_SLAVE_CTRL,  4 },
  76         { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
  77         { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
  78         { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
  79         { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
  80
  81         /* end marker */
  82         { 0, -1 }
  83 };
  84
  85 int dram_init(void)
  86 {
  87 #if defined(CONFIG_TARGET_PCM052)
  88
  89         static const struct ddr3_jedec_timings pcm052_ddr_timings = {
  90                 .tinit             = 5,
  91                 .trst_pwron        = 80000,
  92                 .cke_inactive      = 200000,
  93                 .wrlat             = 5,
  94                 .caslat_lin        = 12,
  95                 .trc               = 6,
  96                 .trrd              = 4,
  97                 .tccd              = 4,
  98                 .tbst_int_interval = 4,
  99                 .tfaw              = 18,
 100                 .trp               = 6,
 101                 .twtr              = 4,
 102                 .tras_min          = 15,
 103                 .tmrd              = 4,
 104                 .trtp              = 4,
 105                 .tras_max          = 14040,
 106                 .tmod              = 12,
 107                 .tckesr            = 4,
 108                 .tcke              = 3,
 109                 .trcd_int          = 6,
 110                 .tras_lockout      = 1,
 111                 .tdal              = 10,
 112                 .bstlen            = 3,
 113                 .tdll              = 512,
 114                 .trp_ab            = 6,
 115                 .tref              = 1542,
 116                 .trfc              = 64,
 117                 .tref_int          = 5,
 118                 .tpdex             = 3,
 119                 .txpdll            = 10,
 120                 .txsnr             = 68,
 121                 .txsr              = 506,
 122                 .cksrx             = 5,
 123                 .cksre             = 5,
 124                 .freq_chg_en       = 1,
 125                 .zqcl              = 256,
 126                 .zqinit            = 512,
 127                 .zqcs              = 64,
 128                 .ref_per_zq        = 64,
 129                 .zqcs_rotate       = 1,
 130                 .aprebit           = 10,
 131                 .cmd_age_cnt       = 255,
 132                 .age_cnt           = 255,
 133                 .q_fullness        = 0,
 134                 .odt_rd_mapcs0     = 1,
 135                 .odt_wr_mapcs0     = 1,
 136                 .wlmrd             = 40,
 137                 .wldqsen           = 25,
 138         };
 139
 140     const int row_diff = 2;
 141
 142 #elif defined(CONFIG_TARGET_BK4R1)
 143
 144         static const struct ddr3_jedec_timings pcm052_ddr_timings = {
 145                 .tinit             = 5,
 146                 .trst_pwron        = 80000,
 147                 .cke_inactive      = 200000,
 148                 .wrlat             = 5,
 149                 .caslat_lin        = 12,
 150                 .trc               = 6,
 151                 .trrd              = 4,
 152                 .tccd              = 4,
 153                 .tbst_int_interval = 0,
 154                 .tfaw              = 16,
 155                 .trp               = 6,
 156                 .twtr              = 4,
 157                 .tras_min          = 15,
 158                 .tmrd              = 4,
 159                 .trtp              = 4,
 160                 .tras_max          = 28080,
 161                 .tmod              = 12,
 162                 .tckesr            = 4,
 163                 .tcke              = 3,
 164                 .trcd_int          = 6,
 165                 .tras_lockout      = 1,
 166                 .tdal              = 12,
 167                 .bstlen            = 3,
 168                 .tdll              = 512,
 169                 .trp_ab            = 6,
 170                 .tref              = 3120,
 171                 .trfc              = 104,
 172                 .tref_int          = 0,
 173                 .tpdex             = 3,
 174                 .txpdll            = 10,
 175                 .txsnr             = 108,
 176                 .txsr              = 512,
 177                 .cksrx             = 5,
 178                 .cksre             = 5,
 179                 .freq_chg_en       = 1,
 180                 .zqcl              = 256,
 181                 .zqinit            = 512,
 182                 .zqcs              = 64,
 183                 .ref_per_zq        = 64,
 184                 .zqcs_rotate       = 1,
 185                 .aprebit           = 10,
 186                 .cmd_age_cnt       = 255,
 187                 .age_cnt           = 255,
 188                 .q_fullness        = 0,
 189                 .odt_rd_mapcs0     = 1,
 190                 .odt_wr_mapcs0     = 1,
 191                 .wlmrd             = 40,
 192                 .wldqsen           = 25,
 193         };
 194
 195     const int row_diff = 1;
 196
 197 #else /* Unknown PCM052 variant */
 198
 199 #error DDR characteristics undefined for this target. Please define them.
 200
 201 #endif
 202
 203         ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
 204                              pcm052_phy_settings, 1, row_diff);
 205
 206         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 207
 208         return 0;
 209 }
 210
 211 static void clock_init(void)
 212 {
 213         struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 214         struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 215
 216         clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 217                         CCM_CCGR0_UART1_CTRL_MASK);
 218         clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
 219                         CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
 220         clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
 221                         CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
 222                         CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
 223                         CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
 224                         CCM_CCGR2_QSPI0_CTRL_MASK);
 225         clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
 226                         CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
 227         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 228                         CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
 229                         CCM_CCGR4_GPC_CTRL_MASK);
 230         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 231                         CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 232         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
 233                         CCM_CCGR7_SDHC1_CTRL_MASK);
 234         clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 235                         CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 236         clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
 237                         CCM_CCGR10_NFC_CTRL_MASK);
 238
 239         clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 240                         ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
 241         clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 242                         ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
 243
 244         clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 245                         CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
 246         clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 247                         CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
 248                         CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
 249                         CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
 250                         CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
 251                         CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
 252                         CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
 253         clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 254                         CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 255                         CCM_CACRR_ARM_CLK_DIV(0));
 256         clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
 257                         CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
 258                         CCM_CSCMR1_QSPI0_CLK_SEL(3) |
 259                         CCM_CSCMR1_NFC_CLK_SEL(0));
 260         clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 261                         CCM_CSCDR1_RMII_CLK_EN);
 262         clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 263                         CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
 264                         CCM_CSCDR2_NFC_EN);
 265         clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
 266                         CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
 267                         CCM_CSCDR3_QSPI0_X2_DIV(1) |
 268                         CCM_CSCDR3_QSPI0_X4_DIV(3) |
 269                         CCM_CSCDR3_NFC_PRE_DIV(5));
 270         clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 271                         CCM_CSCMR2_RMII_CLK_SEL(0));
 272 }
 273
 274 static void mscm_init(void)
 275 {
 276         struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
 277         int i;
 278
 279         for (i = 0; i < MSCM_IRSPRC_NUM; i++)
 280                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 281 }
 282
 283 int board_early_init_f(void)
 284 {
 285         clock_init();
 286         mscm_init();
 287
 288         return 0;
 289 }
 290
 291 int board_init(void)
 292 {
 293         struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
 294
 295         /* address of boot parameters */
 296         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 297
 298         /*
 299          * Enable external 32K Oscillator
 300          *
 301          * The internal clock experiences significant drift
 302          * so we must use the external oscillator in order
 303          * to maintain correct time in the hwclock
 304          */
 305         setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
 306
 307         return 0;
 308 }
 309
 310 int checkboard(void)
 311 {
 312 #ifdef CONFIG_TARGET_BK4R1
 313         puts("Board: BK4r1 (L333)\n");
 314 #else
 315         puts("Board: PCM-052\n");
 316 #endif
 317         return 0;
 318 }