board/phytec/pcm051/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
   6  *
   7  * Copyright (C) 2013 Lemonage Software GmbH
   8  * Author Lars Poeschel <poeschel@lemonage.de>
   9  */
  10
  11 #include <common.h>
  12 #include <env.h>
  13 #include <errno.h>
  14 #include <init.h>
  15 #include <net.h>
  16 #include <spl.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/omap.h>
  20 #include <asm/arch/ddr_defs.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/io.h>
  26 #include <asm/emif.h>
  27 #include <asm/gpio.h>
  28 #include <i2c.h>
  29 #include <miiphy.h>
  30 #include <cpsw.h>
  31 #include "board.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 /* MII mode defines */
  36 #define RMII_RGMII2_MODE_ENABLE 0x49
  37
  38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  39
  40 #ifdef CONFIG_SPL_BUILD
  41
  42 /* DDR RAM defines */
  43 #define DDR_CLK_MHZ             303 /* DDR_DPLL_MULT value */
  44
  45 #define OSC     (V_OSCK/1000000)
  46 const struct dpll_params dpll_ddr = {
  47                 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
  48
  49 const struct dpll_params *get_dpll_ddr_params(void)
  50 {
  51         return &dpll_ddr;
  52 }
  53
  54 #ifdef CONFIG_REV1
  55 const struct ctrl_ioregs ioregs = {
  56         .cm0ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  57         .cm1ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  58         .cm2ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  59         .dt0ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  60         .dt1ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  61 };
  62
  63 static const struct ddr_data ddr3_data = {
  64         .datardsratio0 = MT41J256M8HX15E_RD_DQS,
  65         .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
  66         .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
  67         .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
  68 };
  69
  70 static const struct cmd_control ddr3_cmd_ctrl_data = {
  71         .cmd0csratio = MT41J256M8HX15E_RATIO,
  72         .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  73
  74         .cmd1csratio = MT41J256M8HX15E_RATIO,
  75         .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  76
  77         .cmd2csratio = MT41J256M8HX15E_RATIO,
  78         .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  79 };
  80
  81 static struct emif_regs ddr3_emif_reg_data = {
  82         .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
  83         .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
  84         .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
  85         .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
  86         .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
  87         .zq_config = MT41J256M8HX15E_ZQ_CFG,
  88         .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
  89                                 PHY_EN_DYN_PWRDN,
  90 };
  91
  92 void sdram_init(void)
  93 {
  94         config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
  95                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  96 }
  97 #else
  98 const struct ctrl_ioregs ioregs = {
  99         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 100         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 101         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 102         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 103         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 104 };
 105
 106 static const struct ddr_data ddr3_data = {
 107         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 108         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 109         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 110         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 111 };
 112
 113 static const struct cmd_control ddr3_cmd_ctrl_data = {
 114         .cmd0csratio = MT41K256M16HA125E_RATIO,
 115         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 116
 117         .cmd1csratio = MT41K256M16HA125E_RATIO,
 118         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 119
 120         .cmd2csratio = MT41K256M16HA125E_RATIO,
 121         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 122 };
 123
 124 static struct emif_regs ddr3_emif_reg_data = {
 125         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 126         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 127         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 128         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 129         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 130         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 131         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
 132                                 PHY_EN_DYN_PWRDN,
 133 };
 134
 135 void sdram_init(void)
 136 {
 137         config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
 138                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 139 }
 140 #endif
 141
 142 void set_uart_mux_conf(void)
 143 {
 144         enable_uart0_pin_mux();
 145 }
 146
 147 void set_mux_conf_regs(void)
 148 {
 149         /* Initalize the board header */
 150         enable_i2c0_pin_mux();
 151         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 152
 153         enable_board_pin_mux();
 154 }
 155 #endif
 156
 157 /*
 158  * Basic board specific setup.  Pinmux has been handled already.
 159  */
 160 int board_init(void)
 161 {
 162         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 163
 164         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 165
 166         return 0;
 167 }
 168
 169 #ifdef CONFIG_DRIVER_TI_CPSW
 170 static void cpsw_control(int enabled)
 171 {
 172         /* VTP can be added here */
 173
 174         return;
 175 }
 176
 177 static struct cpsw_slave_data cpsw_slaves[] = {
 178         {
 179                 .slave_reg_ofs  = 0x208,
 180                 .sliver_reg_ofs = 0xd80,
 181                 .phy_addr       = 0,
 182                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 183         },
 184         {
 185                 .slave_reg_ofs  = 0x308,
 186                 .sliver_reg_ofs = 0xdc0,
 187                 .phy_addr       = 1,
 188                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 189         },
 190 };
 191
 192 static struct cpsw_platform_data cpsw_data = {
 193         .mdio_base              = CPSW_MDIO_BASE,
 194         .cpsw_base              = CPSW_BASE,
 195         .mdio_div               = 0xff,
 196         .channels               = 8,
 197         .cpdma_reg_ofs          = 0x800,
 198         .slaves                 = 1,
 199         .slave_data             = cpsw_slaves,
 200         .ale_reg_ofs            = 0xd00,
 201         .ale_entries            = 1024,
 202         .host_port_reg_ofs      = 0x108,
 203         .hw_stats_reg_ofs       = 0x900,
 204         .bd_ram_ofs             = 0x2000,
 205         .mac_control            = (1 << 5),
 206         .control                = cpsw_control,
 207         .host_port_num          = 0,
 208         .version                = CPSW_CTRL_VERSION_2,
 209 };
 210 #endif
 211
 212 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 213         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 214 int board_eth_init(bd_t *bis)
 215 {
 216         int rv, n = 0;
 217 #ifdef CONFIG_DRIVER_TI_CPSW
 218         uint8_t mac_addr[6];
 219         uint32_t mac_hi, mac_lo;
 220
 221         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 222                 printf("<ethaddr> not set. Reading from E-fuse\n");
 223                 /* try reading mac address from efuse */
 224                 mac_lo = readl(&cdev->macid0l);
 225                 mac_hi = readl(&cdev->macid0h);
 226                 mac_addr[0] = mac_hi & 0xFF;
 227                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 228                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 229                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 230                 mac_addr[4] = mac_lo & 0xFF;
 231                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 232
 233                 if (is_valid_ethaddr(mac_addr))
 234                         eth_env_set_enetaddr("ethaddr", mac_addr);
 235                 else
 236                         goto try_usbether;
 237         }
 238
 239         writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
 240
 241         rv = cpsw_register(&cpsw_data);
 242         if (rv < 0)
 243                 printf("Error %d registering CPSW switch\n", rv);
 244         else
 245                 n += rv;
 246 try_usbether:
 247 #endif
 248
 249 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
 250         rv = usb_eth_initialize(bis);
 251         if (rv < 0)
 252                 printf("Error %d registering USB_ETHER\n", rv);
 253         else
 254                 n += rv;
 255 #endif
 256         return n;
 257 }
 258 #endif