1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Collabora Ltd.
5 * Based on board/ccv/xpress/spl.c:
6 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
11 #include <asm/arch/clock.h>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/sys_proto.h>
17 #include <fsl_esdhc_imx.h>
19 /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
21 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
22 .grp_addds = 0x00000030,
23 .grp_ddrmode_ctl = 0x00020000,
24 .grp_b0ds = 0x00000030,
25 .grp_ctlds = 0x00000030,
26 .grp_b1ds = 0x00000030,
27 .grp_ddrpke = 0x00000000,
28 .grp_ddrmode = 0x00020000,
29 .grp_ddr_type = 0x000c0000,
32 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
33 .dram_dqm0 = 0x00000030,
34 .dram_dqm1 = 0x00000030,
35 .dram_ras = 0x00000030,
36 .dram_cas = 0x00000030,
37 .dram_odt0 = 0x00000030,
38 .dram_odt1 = 0x00000030,
39 .dram_sdba2 = 0x00000000,
40 .dram_sdclk_0 = 0x00000030,
41 .dram_sdqs0 = 0x00000030,
42 .dram_sdqs1 = 0x00000030,
43 .dram_reset = 0x00000030,
46 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
47 .p0_mpwldectrl0 = 0x00000000,
48 .p0_mpdgctrl0 = 0x41480148,
49 .p0_mprddlctl = 0x40403E42,
50 .p0_mpwrdlctl = 0x40405852,
53 struct mx6_ddr_sysinfo ddr_sysinfo = {
54 .dsize = 0, /* Bus size = 16bit */
60 .walat = 1, /* Write additional latency */
61 .ralat = 5, /* Read additional latency */
62 .mif3_mode = 3, /* Command prediction working mode */
63 .bi_on = 1, /* Bank interleaving enabled */
65 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
66 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
67 .ddr_type = DDR_TYPE_DDR3,
68 .refsel = 1, /* Refresh cycles at 32KHz */
69 .refr = 7, /* 8 refresh commands per refresh cycle */
72 static struct mx6_ddr3_cfg mem_ddr = {
85 static void ccgr_init(void)
87 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
89 writel(0xFFFFFFFF, &ccm->CCGR0);
90 writel(0xFFFFFFFF, &ccm->CCGR1);
91 writel(0xFFFFFFFF, &ccm->CCGR2);
92 writel(0xFFFFFFFF, &ccm->CCGR3);
93 writel(0xFFFFFFFF, &ccm->CCGR4);
94 writel(0xFFFFFFFF, &ccm->CCGR5);
95 writel(0xFFFFFFFF, &ccm->CCGR6);
98 static void spl_dram_init(void)
100 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
101 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
104 #ifdef CONFIG_FSL_ESDHC_IMX
106 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
107 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
108 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
111 static iomux_v3_cfg_t const usdhc1_pads[] = {
112 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
113 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 #ifndef CONFIG_NAND_MXS
122 static iomux_v3_cfg_t const usdhc2_pads[] = {
123 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 static struct fsl_esdhc_cfg usdhc_cfg[] = {
138 .esdhc_base = USDHC1_BASE_ADDR,
141 #ifndef CONFIG_NAND_MXS
143 .esdhc_base = USDHC2_BASE_ADDR,
149 int board_mmc_getcd(struct mmc *mmc)
154 int board_mmc_init(bd_t *bis)
158 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
161 SETUP_IOMUX_PADS(usdhc1_pads);
162 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
164 #ifndef CONFIG_NAND_MXS
166 SETUP_IOMUX_PADS(usdhc2_pads);
167 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
171 printf("Warning - USDHC%d controller not supporting\n",
176 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
178 printf("Warning: failed to initialize mmc dev %d\n", i);
186 void board_boot_order(u32 *spl_boot_list)
188 u32 bmode = imx6_src_get_boot_mode();
189 u8 boot_dev = BOOT_DEVICE_MMC1;
191 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
194 boot_dev = BOOT_DEVICE_MMC1;
197 case IMX6_BMODE_EMMC:
198 boot_dev = BOOT_DEVICE_MMC2;
200 case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
201 boot_dev = BOOT_DEVICE_NAND;
204 /* Default - BOOT_DEVICE_MMC1 */
205 printf("Wrong board boot order\n");
209 spl_boot_list[0] = boot_dev;
211 #endif /* CONFIG_FSL_ESDHC_IMX */
213 void board_init_f(ulong dummy)
217 /* Setup AIPS and disable watchdog */
220 /* Setup iomux and fec */
221 board_early_init_f();
226 /* UART clocks enabled and gd valid - init serial console */
227 preloader_console_init();
229 /* DDR initialization */