3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <spd_sdram.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
33 static void set_leds(int val)
35 unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
36 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
37 out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27));
40 int board_early_init_f(void)
44 set_leds(0); /* display boot info counter */
46 /*--------------------------------------------------------------------
47 * Setup the external bus controller/chip selects
48 *-------------------------------------------------------------------*/
49 mtdcr(ebccfga, xbcfg);
51 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
53 /*--------------------------------------------------------------------
54 * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
55 * via define from board config file.
56 *-------------------------------------------------------------------*/
58 /*--------------------------------------------------------------------
59 * Setup the interrupt controller polarities, triggers, etc.
60 *-------------------------------------------------------------------*/
61 mtdcr(uic0sr, 0xffffffff); /* clear all */
62 mtdcr(uic0er, 0x00000000); /* disable all */
63 mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
64 mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */
65 mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */
66 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
67 mtdcr(uic0sr, 0xffffffff); /* clear all */
69 mtdcr(uic1sr, 0xffffffff); /* clear all */
70 mtdcr(uic1er, 0x00000000); /* disable all */
71 mtdcr(uic1cr, 0x00000000); /* all non-critical */
72 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
73 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
74 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
75 mtdcr(uic1sr, 0xffffffff); /* clear all */
77 /*--------------------------------------------------------------------
78 * Setup other serial configuration
79 *-------------------------------------------------------------------*/
81 mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
82 mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */
83 mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
88 int misc_init_r (void)
93 /* Re-do sizing to get full correct info */
94 mtdcr(ebccfga, pb0cr);
95 pbcr = mfdcr(ebccfgd);
96 switch (gd->bd->bi_flashsize) {
122 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
123 mtdcr(ebccfga, pb0cr);
124 mtdcr(ebccfgd, pbcr);
126 /* adjust flash start and offset */
127 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
128 gd->bd->bi_flashoffset = 0;
130 /* Monitor protection ON by default */
131 (void)flash_protect(FLAG_PROTECT_SET,
136 /* Env protection ON by default */
137 (void)flash_protect(FLAG_PROTECT_SET,
139 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
147 char *s = getenv("serial#");
149 printf("Board: PCS440EP");
159 long int initdram (int board_type)
163 set_leds(1); /* display boot info counter */
164 dram_size = spd_sdram();
165 set_leds(2); /* display boot info counter */
170 #if defined(CFG_DRAM_TEST)
173 unsigned long *mem = (unsigned long *)0;
174 const unsigned long kend = (1024 / sizeof(unsigned long));
179 for (k = 0; k < CFG_KBYTES_SDRAM;
180 ++k, mem += (1024 / sizeof(unsigned long))) {
181 if ((k & 1023) == 0) {
182 printf("%3d MB\r", k / 1024);
185 memset(mem, 0xaaaaaaaa, 1024);
186 for (n = 0; n < kend; ++n) {
187 if (mem[n] != 0xaaaaaaaa) {
188 printf("SDRAM test fails at: %08x\n",
194 memset(mem, 0x55555555, 1024);
195 for (n = 0; n < kend; ++n) {
196 if (mem[n] != 0x55555555) {
197 printf("SDRAM test fails at: %08x\n",
203 printf("SDRAM test passes\n");
208 /*************************************************************************
211 * This routine is called just prior to registering the hose and gives
212 * the board the opportunity to check things. Returning a value of zero
213 * indicates that things are bad & PCI initialization should be aborted.
215 * Different boards may wish to customize the pci controller structure
216 * (add regions, override default access routines, etc) or perform
217 * certain pre-initialization actions.
219 ************************************************************************/
220 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
221 int pci_pre_init(struct pci_controller *hose)
225 /*-------------------------------------------------------------------------+
226 | Set priority for all PLB3 devices to 0.
227 | Set PLB3 arbiter to fair mode.
228 +-------------------------------------------------------------------------*/
229 mfsdr(sdr_amp1, addr);
230 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
231 addr = mfdcr(plb3_acr);
232 mtdcr(plb3_acr, addr | 0x80000000);
234 /*-------------------------------------------------------------------------+
235 | Set priority for all PLB4 devices to 0.
236 +-------------------------------------------------------------------------*/
237 mfsdr(sdr_amp0, addr);
238 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
239 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
240 mtdcr(plb4_acr, addr);
242 /*-------------------------------------------------------------------------+
243 | Set Nebula PLB4 arbiter to fair mode.
244 +-------------------------------------------------------------------------*/
246 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
247 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
248 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
249 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
250 mtdcr(plb0_acr, addr);
253 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
254 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
255 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
256 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
257 mtdcr(plb1_acr, addr);
261 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
263 /*************************************************************************
266 * The bootstrap configuration provides default settings for the pci
267 * inbound map (PIM). But the bootstrap config choices are limited and
268 * may not be sufficient for a given board.
270 ************************************************************************/
271 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
272 void pci_target_init(struct pci_controller *hose)
274 /*--------------------------------------------------------------------------+
275 * Set up Direct MMIO registers
276 *--------------------------------------------------------------------------*/
277 /*--------------------------------------------------------------------------+
278 | PowerPC440 EP PCI Master configuration.
279 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
280 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
281 | Use byte reversed out routines to handle endianess.
282 | Make this region non-prefetchable.
283 +--------------------------------------------------------------------------*/
284 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
285 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
286 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
287 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
288 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
290 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
291 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
292 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
293 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
294 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
296 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
297 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
298 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
299 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
301 /*--------------------------------------------------------------------------+
302 * Set up Configuration registers
303 *--------------------------------------------------------------------------*/
305 /* Program the board's subsystem id/vendor id */
306 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
307 CFG_PCI_SUBSYS_VENDORID);
308 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
310 /* Configure command register as bus master */
311 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
313 /* 240nS PCI clock */
314 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
316 /* No error reporting */
317 pci_write_config_word(0, PCI_ERREN, 0);
319 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
322 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
324 /*************************************************************************
327 ************************************************************************/
328 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
329 void pci_master_init(struct pci_controller *hose)
331 unsigned short temp_short;
333 /*--------------------------------------------------------------------------+
334 | Write the PowerPC440 EP PCI Configuration regs.
335 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
336 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
337 +--------------------------------------------------------------------------*/
338 pci_read_config_word(0, PCI_COMMAND, &temp_short);
339 pci_write_config_word(0, PCI_COMMAND,
340 temp_short | PCI_COMMAND_MASTER |
343 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
345 /*************************************************************************
348 * This routine is called to determine if a pci scan should be
349 * performed. With various hardware environments (especially cPCI and
350 * PPMC) it's insufficient to depend on the state of the arbiter enable
351 * bit in the strap register, or generic host/adapter assumptions.
353 * Rather than hard-code a bad assumption in the general 440 code, the
354 * 440 pci code requires the board to decide at runtime.
356 * Return 0 for adapter mode, non-zero for host (monarch) mode.
359 ************************************************************************/
360 #if defined(CONFIG_PCI)
361 int is_pci_host(struct pci_controller *hose)
363 /* PCS440EP is always configured as host. */
366 #endif /* defined(CONFIG_PCI) */
368 /*************************************************************************
371 * This routine is called to reset (keep alive) the watchdog timer
373 ************************************************************************/
374 #if defined(CONFIG_HW_WATCHDOG)
375 void hw_watchdog_reset(void)