2 * Copyright (C) 2004 PaulReynolds@lhsolutions.com
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <spd_sdram.h>
28 #include <440gx_enet.h>
30 #define BOOT_SMALL_FLASH 32 /* 00100000 */
31 #define FLASH_ONBD_N 2 /* 00000010 */
32 #define FLASH_SRAM_SEL 1 /* 00000001 */
34 long int fixed_sdram (void);
35 void fpga_init (void);
37 int board_early_init_f (void)
39 /*-------------------------------------------------------------------------+
40 | Initialize EBC CONFIG
41 +-------------------------------------------------------------------------*/
42 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
43 EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
44 EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
45 EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
46 EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
48 /*-------------------------------------------------------------------------+
49 | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
50 +-------------------------------------------------------------------------*/
51 mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)|
53 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
54 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
55 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
56 EBC_BXAP_BEM_WRITEONLY|
57 EBC_BXAP_PEN_DISABLED);
58 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)|
59 EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
61 /*-------------------------------------------------------------------------+
62 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
63 +-------------------------------------------------------------------------*/
64 mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
66 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
67 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
68 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
69 EBC_BXAP_BEM_WRITEONLY|
70 EBC_BXAP_PEN_DISABLED);
71 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
72 EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
74 /*-------------------------------------------------------------------------+
75 | 4 MB FLASH. Initialize bank 2 with default values.
76 +-------------------------------------------------------------------------*/
77 mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
79 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
80 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
81 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
82 EBC_BXAP_BEM_WRITEONLY|
83 EBC_BXAP_PEN_DISABLED);
84 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)|
85 EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
87 /*-------------------------------------------------------------------------+
88 | FPGA. Initialize bank 7 with default values.
89 +-------------------------------------------------------------------------*/
90 mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
92 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
93 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
94 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
95 EBC_BXAP_BEM_WRITEONLY|
96 EBC_BXAP_PEN_DISABLED);
97 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
98 EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
100 /*--------------------------------------------------------------------
101 * Setup the interrupt controller polarities, triggers, etc.
102 *-------------------------------------------------------------------*/
103 mtdcr (uic0sr, 0xffffffff); /* clear all */
104 mtdcr (uic0er, 0x00000000); /* disable all */
105 mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
106 mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
107 mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
108 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
109 mtdcr (uic0sr, 0xffffffff); /* clear all */
111 mtdcr (uic1sr, 0xffffffff); /* clear all */
112 mtdcr (uic1er, 0x00000000); /* disable all */
113 mtdcr (uic1cr, 0x00000000); /* all non-critical */
114 mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
115 mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
116 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
117 mtdcr (uic1sr, 0xffffffff); /* clear all */
125 int checkboard (void)
129 get_sys_info (&sysinfo);
131 printf ("Board: IBM 440GX Evaluation Board\n");
132 printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
133 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
134 printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
135 printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
136 printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
141 long int initdram (int board_type)
145 #if defined(CONFIG_SPD_EEPROM)
146 dram_size = spd_sdram (0);
148 dram_size = fixed_sdram ();
154 #if defined(CFG_DRAM_TEST)
157 uint *pstart = (uint *) 0x00000000;
158 uint *pend = (uint *) 0x08000000;
161 for (p = pstart; p < pend; p++)
164 for (p = pstart; p < pend; p++) {
165 if (*p != 0xaaaaaaaa) {
166 printf ("SDRAM test fails at: %08x\n", (uint) p);
171 for (p = pstart; p < pend; p++)
174 for (p = pstart; p < pend; p++) {
175 if (*p != 0x55555555) {
176 printf ("SDRAM test fails at: %08x\n", (uint) p);
184 #if !defined(CONFIG_SPD_EEPROM)
185 /*************************************************************************
186 * fixed sdram init -- doesn't use serial presence detect.
188 * Assumes: 128 MB, non-ECC, non-registered
191 ************************************************************************/
192 long int fixed_sdram (void)
196 /*--------------------------------------------------------------------
198 *------------------------------------------------------------------*/
199 mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
200 mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
201 mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
202 mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
203 mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
205 /*--------------------------------------------------------------------
206 * Setup for board-specific specific mem
207 *------------------------------------------------------------------*/
209 * Following for CAS Latency = 2.5 @ 133 MHz PLB
211 mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
212 mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
214 mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
215 mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
216 mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
217 udelay (400); /* Delay 200 usecs (min) */
219 /*--------------------------------------------------------------------
220 * Enable the controller, then wait for DCEN to complete
221 *------------------------------------------------------------------*/
222 mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
224 mfsdram (mem_mcsts, reg);
225 if (reg & 0x80000000)
229 return (128 * 1024 * 1024); /* 128 MB */
231 #endif /* !defined(CONFIG_SPD_EEPROM) */
234 /*************************************************************************
237 * This routine is called just prior to registering the hose and gives
238 * the board the opportunity to check things. Returning a value of zero
239 * indicates that things are bad & PCI initialization should be aborted.
241 * Different boards may wish to customize the pci controller structure
242 * (add regions, override default access routines, etc) or perform
243 * certain pre-initialization actions.
245 ************************************************************************/
246 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
247 int pci_pre_init(struct pci_controller * hose )
251 /*--------------------------------------------------------------------------+
252 * The ocotea board is always configured as the host & requires the
253 * PCI arbiter to be enabled.
254 *--------------------------------------------------------------------------*/
255 mfsdr(sdr_sdstp1, strap);
256 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
257 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
263 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
265 /*************************************************************************
268 * The bootstrap configuration provides default settings for the pci
269 * inbound map (PIM). But the bootstrap config choices are limited and
270 * may not be sufficient for a given board.
272 ************************************************************************/
273 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
274 void pci_target_init(struct pci_controller * hose )
276 DECLARE_GLOBAL_DATA_PTR;
278 /*--------------------------------------------------------------------------+
280 *--------------------------------------------------------------------------*/
281 out32r( PCIX0_PIM0SA, 0 ); /* disable */
282 out32r( PCIX0_PIM1SA, 0 ); /* disable */
283 out32r( PCIX0_PIM2SA, 0 ); /* disable */
284 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
286 /*--------------------------------------------------------------------------+
287 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
288 * options to not support sizes such as 128/256 MB.
289 *--------------------------------------------------------------------------*/
290 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
291 out32r( PCIX0_PIM0LAH, 0 );
292 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
294 out32r( PCIX0_BAR0, 0 );
296 /*--------------------------------------------------------------------------+
297 * Program the board's subsystem id/vendor id
298 *--------------------------------------------------------------------------*/
299 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
300 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
302 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
304 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
307 /*************************************************************************
310 * This routine is called to determine if a pci scan should be
311 * performed. With various hardware environments (especially cPCI and
312 * PPMC) it's insufficient to depend on the state of the arbiter enable
313 * bit in the strap register, or generic host/adapter assumptions.
315 * Rather than hard-code a bad assumption in the general 440 code, the
316 * 440 pci code requires the board to decide at runtime.
318 * Return 0 for adapter mode, non-zero for host (monarch) mode.
321 ************************************************************************/
322 #if defined(CONFIG_PCI)
323 int is_pci_host(struct pci_controller *hose)
325 /* The ocotea board is always configured as host. */
328 #endif /* defined(CONFIG_PCI) */
334 unsigned long sdr0_pfc0;
335 unsigned long sdr0_pfc1;
336 unsigned long sdr0_cust0;
339 mfsdr (sdr_pfc0, sdr0_pfc0);
340 mfsdr (sdr_pfc1, sdr0_pfc1);
341 group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
344 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
345 if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
346 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
347 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
348 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
349 FPGA_REG2_EXT_INTFACE_ENABLE);
350 mtsdr (sdr_pfc0, sdr0_pfc0);
351 mtsdr (sdr_pfc1, sdr0_pfc1);
353 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
360 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
361 FPGA_REG2_EXT_INTFACE_ENABLE);
362 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
363 mtsdr (sdr_pfc0, sdr0_pfc0);
364 mtsdr (sdr_pfc1, sdr0_pfc1);
370 /* CPU trace B - Over EBMI */
371 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
372 mtsdr (sdr_pfc0, sdr0_pfc0);
373 mtsdr (sdr_pfc1, sdr0_pfc1);
374 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
375 FPGA_REG2_EXT_INTFACE_DISABLE);
380 /* Initialize the ethernet specific functions in the fpga */
381 mfsdr(sdr_pfc1, sdr0_pfc1);
382 mfsdr(sdr_cust0, sdr0_cust0);
383 if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
384 ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
385 (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
387 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
389 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
390 FPGA_REG3_ENET_GROUP7);
394 if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
396 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
397 FPGA_REG3_ENET_GROUP7);
401 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
402 FPGA_REG3_ENET_GROUP8);
408 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
410 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
411 FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
415 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
416 FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
419 out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
420 FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
421 FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
423 /* reset the gigabyte phy if necessary */
424 if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
426 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
428 out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
430 out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
434 out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
436 out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
440 /* Turn off the LED's */
441 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
442 FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
443 FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
450 * Returns 1 if keys pressed to start the power-on long-running tests
451 * Called from board_init_f().
453 int post_hotkeys_pressed(void)