2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/tegra2.h>
28 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/clk_rst.h>
31 #include <asm/arch/pinmux.h>
32 #include <asm/arch/uart.h>
35 #ifdef CONFIG_TEGRA2_MMC
39 DECLARE_GLOBAL_DATA_PTR;
41 const struct tegra2_sysinfo sysinfo = {
42 CONFIG_TEGRA2_BOARD_STRING
45 #ifdef CONFIG_BOARD_EARLY_INIT_F
46 int board_early_init_f(void)
48 /* Initialize periph clocks */
51 /* Initialize periph pinmuxes */
54 /* Initialize periph GPIOs */
57 /* Init UART, scratch regs, and start CPU */
61 #endif /* EARLY_INIT */
65 * Description: init the timestamp and lastinc value
73 * Routine: clock_init_uart
74 * Description: init the PLL and clock for the UART(s)
76 static void clock_init_uart(void)
78 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
81 reg = readl(&clkrst->crc_pllp_base);
82 if (!(reg & PLL_BASE_OVRRIDE)) {
83 /* Override pllp setup for 216MHz operation. */
84 reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
85 reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
86 writel(reg, &clkrst->crc_pllp_base);
89 writel(reg, &clkrst->crc_pllp_base);
92 writel(reg, &clkrst->crc_pllp_base);
95 /* Now do the UART reset/clock enable */
96 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
97 /* Assert Reset to UART */
98 reg = readl(&clkrst->crc_rst_dev_l);
99 reg |= SWR_UARTA_RST; /* SWR_UARTA_RST = 1 */
100 writel(reg, &clkrst->crc_rst_dev_l);
102 /* Enable clk to UART */
103 reg = readl(&clkrst->crc_clk_out_enb_l);
104 reg |= CLK_ENB_UARTA; /* CLK_ENB_UARTA = 1 */
105 writel(reg, &clkrst->crc_clk_out_enb_l);
107 /* Enable pllp_out0 to UART */
108 reg = readl(&clkrst->crc_clk_src_uarta);
109 reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
110 writel(reg, &clkrst->crc_clk_src_uarta);
115 /* De-assert reset to UART */
116 reg = readl(&clkrst->crc_rst_dev_l);
117 reg &= ~SWR_UARTA_RST; /* SWR_UARTA_RST = 0 */
118 writel(reg, &clkrst->crc_rst_dev_l);
119 #endif /* CONFIG_TEGRA2_ENABLE_UARTA */
120 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
121 /* Assert Reset to UART */
122 reg = readl(&clkrst->crc_rst_dev_u);
123 reg |= SWR_UARTD_RST; /* SWR_UARTD_RST = 1 */
124 writel(reg, &clkrst->crc_rst_dev_u);
126 /* Enable clk to UART */
127 reg = readl(&clkrst->crc_clk_out_enb_u);
128 reg |= CLK_ENB_UARTD; /* CLK_ENB_UARTD = 1 */
129 writel(reg, &clkrst->crc_clk_out_enb_u);
131 /* Enable pllp_out0 to UART */
132 reg = readl(&clkrst->crc_clk_src_uartd);
133 reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
134 writel(reg, &clkrst->crc_clk_src_uartd);
139 /* De-assert reset to UART */
140 reg = readl(&clkrst->crc_rst_dev_u);
141 reg &= ~SWR_UARTD_RST; /* SWR_UARTD_RST = 0 */
142 writel(reg, &clkrst->crc_rst_dev_u);
143 #endif /* CONFIG_TEGRA2_ENABLE_UARTD */
147 * Routine: pin_mux_uart
148 * Description: setup the pin muxes/tristate values for the UART(s)
150 static void pin_mux_uart(void)
152 struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
155 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
156 reg = readl(&pmt->pmt_ctl_c);
157 reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
158 writel(reg, &pmt->pmt_ctl_c);
160 reg = readl(&pmt->pmt_tri_a);
161 reg &= ~Z_IRRX; /* Z_IRRX = normal (0) */
162 reg &= ~Z_IRTX; /* Z_IRTX = normal (0) */
163 writel(reg, &pmt->pmt_tri_a);
164 #endif /* CONFIG_TEGRA2_ENABLE_UARTA */
165 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
166 reg = readl(&pmt->pmt_ctl_b);
167 reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
168 writel(reg, &pmt->pmt_ctl_b);
170 reg = readl(&pmt->pmt_tri_a);
171 reg &= ~Z_GMC; /* Z_GMC = normal (0) */
172 writel(reg, &pmt->pmt_tri_a);
173 #endif /* CONFIG_TEGRA2_ENABLE_UARTD */
177 * Routine: clock_init_mmc
178 * Description: init the PLL and clocks for the SDMMC controllers
180 static void clock_init_mmc(void)
182 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
185 /* Do the SDMMC resets/clock enables */
187 /* Assert Reset to SDMMC4 */
188 reg = readl(&clkrst->crc_rst_dev_l);
189 reg |= SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 1 */
190 writel(reg, &clkrst->crc_rst_dev_l);
192 /* Enable clk to SDMMC4 */
193 reg = readl(&clkrst->crc_clk_out_enb_l);
194 reg |= CLK_ENB_SDMMC4; /* CLK_ENB_SDMMC4 = 1 */
195 writel(reg, &clkrst->crc_clk_out_enb_l);
197 /* Enable pllp_out0 to SDMMC4 */
198 reg = readl(&clkrst->crc_clk_src_sdmmc4);
199 reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
200 reg |= (10 << 1); /* n-1, 11-1 shl 1 */
201 writel(reg, &clkrst->crc_clk_src_sdmmc4);
204 * As per the Tegra2 TRM, section 5.3.4:
205 * 'Wait 2 us for the clock to flush through the pipe/logic'
209 /* De-assert reset to SDMMC4 */
210 reg = readl(&clkrst->crc_rst_dev_l);
211 reg &= ~SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 0 */
212 writel(reg, &clkrst->crc_rst_dev_l);
214 /* Assert Reset to SDMMC3 */
215 reg = readl(&clkrst->crc_rst_dev_u);
216 reg |= SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 1 */
217 writel(reg, &clkrst->crc_rst_dev_u);
219 /* Enable clk to SDMMC3 */
220 reg = readl(&clkrst->crc_clk_out_enb_u);
221 reg |= CLK_ENB_SDMMC3; /* CLK_ENB_SDMMC3 = 1 */
222 writel(reg, &clkrst->crc_clk_out_enb_u);
224 /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
225 reg = readl(&clkrst->crc_clk_src_sdmmc3);
226 reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
227 reg |= (10 << 1); /* n-1, 11-1 shl 1 */
228 writel(reg, &clkrst->crc_clk_src_sdmmc3);
233 /* De-assert reset to SDMMC3 */
234 reg = readl(&clkrst->crc_rst_dev_u);
235 reg &= ~SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 0 */
236 writel(reg, &clkrst->crc_rst_dev_u);
240 * Routine: pin_mux_mmc
241 * Description: setup the pin muxes/tristate values for the SDMMC(s)
243 static void pin_mux_mmc(void)
245 struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
249 /* config 2, x8 on 2nd set of pins */
250 reg = readl(&pmt->pmt_ctl_a);
251 reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */
252 writel(reg, &pmt->pmt_ctl_a);
253 reg = readl(&pmt->pmt_ctl_b);
254 reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */
255 writel(reg, &pmt->pmt_ctl_b);
256 reg = readl(&pmt->pmt_ctl_d);
257 reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
258 writel(reg, &pmt->pmt_ctl_d);
260 reg = readl(&pmt->pmt_tri_a);
261 reg &= ~Z_ATB; /* Z_ATB = normal (0) */
262 reg &= ~Z_GMA; /* Z_GMA = normal (0) */
263 writel(reg, &pmt->pmt_tri_a);
264 reg = readl(&pmt->pmt_tri_b);
265 reg &= ~Z_GME; /* Z_GME = normal (0) */
266 writel(reg, &pmt->pmt_tri_b);
269 /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
270 reg = readl(&pmt->pmt_ctl_d);
272 reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */
273 reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */
274 reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
275 writel(reg, &pmt->pmt_ctl_d);
277 reg = readl(&pmt->pmt_tri_b);
278 reg &= ~Z_SDC; /* Z_SDC = normal (0) */
279 reg &= ~Z_SDD; /* Z_SDD = normal (0) */
280 writel(reg, &pmt->pmt_tri_b);
281 reg = readl(&pmt->pmt_tri_d);
282 reg &= ~Z_SDB; /* Z_SDB = normal (0) */
283 writel(reg, &pmt->pmt_tri_d);
287 * Routine: clock_init
288 * Description: Do individual peripheral clock reset/enables
290 void clock_init(void)
296 * Routine: pinmux_init
297 * Description: Do individual peripheral pinmux configs
299 void pinmux_init(void)
306 * Description: Do individual peripheral GPIO configs
314 * Routine: board_init
315 * Description: Early hardware init.
319 /* boot param addr */
320 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
321 /* board id for Linux */
322 gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
327 #ifdef CONFIG_TEGRA2_MMC
328 /* this is a weak define that we are overriding */
329 int board_mmc_init(bd_t *bd)
331 debug("board_mmc_init called\n");
332 /* Enable clocks, muxes, etc. for SDMMC controllers */
336 debug("board_mmc_init: init eMMC\n");
337 /* init dev 0, eMMC chip, with 4-bit bus */
338 tegra2_mmc_init(0, 4);
340 debug("board_mmc_init: init SD slot\n");
341 /* init dev 1, SD slot, with 4-bit bus */
342 tegra2_mmc_init(1, 4);
347 /* this is a weak define that we are overriding */
348 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
350 debug("board_mmc_getcd called\n");
352 * Hard-code CD presence for now. Need to add GPIO inputs
353 * for Seaboard & Harmony (& Kaen/Aebl/Wario?)