2 *(C) Copyright 2005-2007 Netstal Maschinen AG
3 * Niklaus Giger (Niklaus.Giger@netstal.com)
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
22 #include <asm/processor.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 void sysLedSet(u32 value);
30 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
32 #undef BOOTSTRAP_OPTION_A_ACTIVE
34 #define SDR0_CP440 0x0180
36 #define SYSTEM_RESET 0x30000000
37 #define CHIP_RESET 0x20000000
39 #define SDR0_ECID0 0x0080
40 #define SDR0_ECID1 0x0081
41 #define SDR0_ECID2 0x0082
42 #define SDR0_ECID3 0x0083
44 #define SYS_IO_ADDRESS 0xcce00000
46 #define DEFAULT_ETH_ADDR "ethaddr"
47 /* ethaddr for first or etha1ddr for second ethernet */
50 /* HW_GENERATION_HCU1 is no longer supported */
51 HW_GENERATION_HCU2 = 0x10,
52 HW_GENERATION_HCU3 = 0x10,
53 HW_GENERATION_HCU4 = 0x20,
54 HW_GENERATION_HCU5 = 0x30,
55 HW_GENERATION_MCU = 0x08,
56 HW_GENERATION_MCU20 = 0x0a,
57 HW_GENERATION_MCU25 = 0x09,
62 * This function is run very early, out of flash, and before devices are
63 * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
64 * of being in the init_sequence array.
66 * The SDRAM has been initialized already -- start.S:start called
67 * init.S:init_sdram early on -- but it is not yet being used for
68 * anything, not even stack. So be careful.
71 int board_early_init_f(void)
75 #ifdef BOOTSTRAP_OPTION_A_ACTIVE
76 /* Booting with Bootstrap Option A
77 * First boot, with CPR0_ICFG_RLI_MASK == 0
78 * no we setup varios boot strapping register,
79 * then we do reset the PPC440 using a chip reset
80 * Unfortunately, we cannot use this option, as Nto1 is not set
81 * with Bootstrap Option A and cannot be changed later on by SW
82 * There are no other possible boostrap options with a 8 bit ROM
83 * See Errata (Version 1.04) CHIP_9
89 mfcpr(CPR0_ICFG, cpr0icfg);
90 if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
91 mtcpr(CPR0_MALD, 0x02000000);
92 mtcpr(CPR0_OPBD, 0x02000000);
93 mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
94 mtcpr(CPR0_PLLC, 0x40000238);
95 mtcpr(CPR0_PLLD, 0x01010414);
96 mtcpr(CPR0_PRIMAD, 0x01000000);
97 mtcpr(CPR0_PRIMBD, 0x01000000);
98 mtcpr(CPR0_SPCID, 0x03000000);
99 mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
100 mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
101 mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
104 * Initiate system reset in debug control register DBCR
107 mtspr(dbcr0, dbcr | CHIP_RESET);
109 mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
111 mtdcr(ebccfga, xbcfg);
112 mtdcr(ebccfgd, 0xb8400000);
114 /*--------------------------------------------------------------------
115 * Setup the GPIO pins
116 *-------------------------------------------------------------------*/
117 /* test-only: take GPIO init from pcs440ep ???? in config file */
118 out32(GPIO0_OR, 0x00000000);
119 out32(GPIO0_TCR, 0x7C2FF1CF);
120 out32(GPIO0_OSRL, 0x40055000);
121 out32(GPIO0_OSRH, 0x00000000);
122 out32(GPIO0_TSRL, 0x40055000);
123 out32(GPIO0_TSRH, 0x00000400);
124 out32(GPIO0_ISR1L, 0x40000000);
125 out32(GPIO0_ISR1H, 0x00000000);
126 out32(GPIO0_ISR2L, 0x00000000);
127 out32(GPIO0_ISR2H, 0x00000000);
128 out32(GPIO0_ISR3L, 0x00000000);
129 out32(GPIO0_ISR3H, 0x00000000);
131 out32(GPIO1_OR, 0x00000000);
132 out32(GPIO1_TCR, 0xC6007FFF);
133 out32(GPIO1_OSRL, 0x00140000);
134 out32(GPIO1_OSRH, 0x00000000);
135 out32(GPIO1_TSRL, 0x00000000);
136 out32(GPIO1_TSRH, 0x00000000);
137 out32(GPIO1_ISR1L, 0x05415555);
138 out32(GPIO1_ISR1H, 0x40000000);
139 out32(GPIO1_ISR2L, 0x00000000);
140 out32(GPIO1_ISR2H, 0x00000000);
141 out32(GPIO1_ISR3L, 0x00000000);
142 out32(GPIO1_ISR3H, 0x00000000);
144 /*--------------------------------------------------------------------
145 * Setup the interrupt controller polarities, triggers, etc.
146 *-------------------------------------------------------------------*/
147 mtdcr(uic0sr, 0xffffffff); /* clear all */
148 mtdcr(uic0er, 0x00000000); /* disable all */
149 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
150 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
151 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
152 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
153 mtdcr(uic0sr, 0xffffffff); /* clear all */
155 mtdcr(uic1sr, 0xffffffff); /* clear all */
156 mtdcr(uic1er, 0x00000000); /* disable all */
157 mtdcr(uic1cr, 0x00000000); /* all non-critical */
158 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
159 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
160 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
161 mtdcr(uic1sr, 0xffffffff); /* clear all */
163 mtdcr(uic2sr, 0xffffffff); /* clear all */
164 mtdcr(uic2er, 0x00000000); /* disable all */
165 mtdcr(uic2cr, 0x00000000); /* all non-critical */
166 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
167 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
168 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
169 mtdcr(uic2sr, 0xffffffff); /* clear all */
170 mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
171 mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
173 /* PCI arbiter enabled */
174 mfsdr(sdr_pci0, reg);
175 mtsdr(sdr_pci0, 0x80000000 | reg);
179 /* setup BOOT FLASH */
180 mtsdr(SDR0_CUST0, 0xC0082350);
185 int board_pre_init(void)
187 return board_early_init_f();
193 u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
194 u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
195 u16 generation = *boardVersReg & 0xf0;
196 u16 index = *boardVersReg & 0x0f;
197 u32 ecid0, ecid1, ecid2, ecid3;
199 printf("Netstal Maschinen AG: ");
200 if (generation == HW_GENERATION_HCU3)
201 printf("HCU3: index %d", index);
202 else if (generation == HW_GENERATION_HCU4)
203 printf("HCU4: index %d", index);
204 else if (generation == HW_GENERATION_HCU5)
205 printf("HCU5: index %d", index);
206 printf(" HW 0x%02x\n", *hwVersReg & 0xff);
207 mfsdr(SDR0_ECID0, ecid0);
208 mfsdr(SDR0_ECID1, ecid1);
209 mfsdr(SDR0_ECID2, ecid2);
210 mfsdr(SDR0_ECID3, ecid3);
212 printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
213 for (j = 0;j < 6; j++) {
223 return in16(SYS_IO_ADDRESS) & 0x3f;
226 void sysLedSet(u32 value /* value to place in LEDs */)
228 out16(SYS_IO_ADDRESS, value);
231 /*---------------------------------------------------------------------------+
233 *---------------------------------------------------------------------------*/
234 static u32 getSerialNr(void)
236 u32 *serial = (u32 *)CFG_FLASH_BASE;
238 if (*serial == 0xffffffff)
245 /*---------------------------------------------------------------------------+
247 *---------------------------------------------------------------------------*/
248 int misc_init_r(void)
250 char *s = getenv(DEFAULT_ETH_ADDR);
253 u32 serial = getSerialNr();
254 unsigned long usb2d0cr = 0;
255 unsigned long usb2phy0cr, usb2h0cr = 0;
256 unsigned long sdr0_pfc1;
258 for (i = 0; i < 6; ++i) {
259 gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
261 s = (*e) ? e + 1 : e;
264 if (gd->bd->bi_enetaddr[3] == 0 &&
265 gd->bd->bi_enetaddr[4] == 0 &&
266 gd->bd->bi_enetaddr[5] == 0) {
269 /* Must be in sync with CONFIG_ETHADDR */
270 gd->bd->bi_enetaddr[0] = 0x00;
271 gd->bd->bi_enetaddr[1] = 0x60;
272 gd->bd->bi_enetaddr[2] = 0x13;
273 gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
274 gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
275 /* byte[5].bit 0 must be zero */
276 gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe;
277 sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
278 gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
279 gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
280 gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
281 printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
283 setenv(DEFAULT_ETH_ADDR, ethaddr);
286 #ifdef CFG_ENV_IS_IN_FLASH
287 /* Monitor protection ON by default */
288 (void)flash_protect(FLAG_PROTECT_SET,
293 /* Env protection ON by default */
294 (void)flash_protect(FLAG_PROTECT_SET,
296 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
305 mfsdr(SDR0_PFC1, sdr0_pfc1);
306 mfsdr(SDR0_USB2D0CR, usb2d0cr);
307 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
308 mfsdr(SDR0_USB2H0CR, usb2h0cr);
310 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
311 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
312 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
313 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
314 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
315 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
316 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
317 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
318 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
319 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
321 /* An 8-bit/60MHz interface is the only possible alternative
322 when connecting the Device to the PHY */
323 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
324 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
326 /* To enable the USB 2.0 Device function through the UTMI interface */
327 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
328 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
330 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
331 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
333 mtsdr(SDR0_PFC1, sdr0_pfc1);
334 mtsdr(SDR0_USB2D0CR, usb2d0cr);
335 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
336 mtsdr(SDR0_USB2H0CR, usb2h0cr);
340 mtsdr(SDR0_SRST1, 0x00000000);
342 mtsdr(SDR0_SRST0, 0x00000000);
344 printf("USB: Host(int phy) Device(ext phy)\n");
349 /*************************************************************************
352 * This routine is called just prior to registering the hose and gives
353 * the board the opportunity to check things. Returning a value of zero
354 * indicates that things are bad & PCI initialization should be aborted.
356 * Different boards may wish to customize the pci controller structure
357 * (add regions, override default access routines, etc) or perform
358 * certain pre-initialization actions.
360 ************************************************************************/
361 #if defined(CONFIG_PCI)
362 int pci_pre_init(struct pci_controller *hose)
366 /*-------------------------------------------------------------------+
367 * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
368 * Workaround: Disable write pipelining to DDR SDRAM by setting
370 *-------------------------------------------------------------------*/
372 /*-------------------------------------------------------------------+
373 | Set priority for all PLB3 devices to 0.
374 | Set PLB3 arbiter to fair mode.
375 +-------------------------------------------------------------------*/
376 mfsdr(sdr_amp1, addr);
377 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
378 addr = mfdcr(plb3_acr);
379 /* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
380 mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
382 /*-------------------------------------------------------------------+
383 | Set priority for all PLB4 devices to 0.
384 +-------------------------------------------------------------------*/
385 mfsdr(sdr_amp0, addr);
386 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
387 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
388 /* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
389 mtdcr(plb4_acr, addr); /* Sequoia */
391 /*-------------------------------------------------------------------+
392 | Set Nebula PLB4 arbiter to fair mode.
393 +-------------------------------------------------------------------*/
395 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
396 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
397 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
398 /* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
399 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
401 /* mtdcr(plb0_acr, addr); */ /* Sequoia */
402 mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
405 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
406 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
407 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
408 addr = (addr & ~plb1_acr_wrp_mask) ;
409 /* mtdcr(plb1_acr, addr); */ /* Sequoia */
410 mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
414 #endif /* defined(CONFIG_PCI) */
416 /*************************************************************************
419 * The bootstrap configuration provides default settings for the pci
420 * inbound map (PIM). But the bootstrap config choices are limited and
421 * may not be sufficient for a given board.
423 ************************************************************************/
424 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
425 void pci_target_init(struct pci_controller *hose)
427 /*-------------------------------------------------------------+
428 * Set up Direct MMIO registers
429 *-------------------------------------------------------------*/
430 /*-------------------------------------------------------------+
431 | PowerPC440EPX PCI Master configuration.
432 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
433 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
434 | 0xA0000000-0xDFFFFFFF
435 | Use byte reversed out routines to handle endianess.
436 | Make this region non-prefetchable.
437 +-------------------------------------------------------------*/
438 /* PMM0 Mask/Attribute - disabled b4 setting */
439 out32r(PCIX0_PMM0MA, 0x00000000);
440 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
441 /* PMM0 PCI Low Address */
442 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
443 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
444 /* 512M + No prefetching, and enable region */
445 out32r(PCIX0_PMM0MA, 0xE0000001);
447 /* PMM0 Mask/Attribute - disabled b4 setting */
448 out32r(PCIX0_PMM1MA, 0x00000000);
449 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
450 /* PMM0 PCI Low Address */
451 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
452 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
453 /* 512M + No prefetching, and enable region */
454 out32r(PCIX0_PMM1MA, 0xE0000001);
456 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
457 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
458 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
459 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
461 /*------------------------------------------------------------------+
462 * Set up Configuration registers
463 *------------------------------------------------------------------*/
465 /* Program the board's subsystem id/vendor id */
466 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
467 CFG_PCI_SUBSYS_VENDORID);
468 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
470 /* Configure command register as bus master */
471 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
473 /* 240nS PCI clock */
474 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
476 /* No error reporting */
477 pci_write_config_word(0, PCI_ERREN, 0);
479 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
481 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
483 /*************************************************************************
486 ************************************************************************/
487 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
488 void pci_master_init(struct pci_controller *hose)
490 unsigned short temp_short;
492 /*---------------------------------------------------------------+
493 | Write the PowerPC440 EP PCI Configuration regs.
494 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
495 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
496 +--------------------------------------------------------------*/
497 pci_read_config_word(0, PCI_COMMAND, &temp_short);
498 pci_write_config_word(0, PCI_COMMAND,
499 temp_short | PCI_COMMAND_MASTER |
503 /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
505 /*************************************************************************
508 * This routine is called to determine if a pci scan should be
509 * performed. With various hardware environments (especially cPCI and
510 * PPMC) it's insufficient to depend on the state of the arbiter enable
511 * bit in the strap register, or generic host/adapter assumptions.
513 * Rather than hard-code a bad assumption in the general 440 code, the
514 * 440 pci code requires the board to decide at runtime.
516 * Return 0 for adapter mode, non-zero for host (monarch) mode.
519 ************************************************************************/
520 #if defined(CONFIG_PCI)
521 int is_pci_host(struct pci_controller *hose)
525 #endif /* defined(CONFIG_PCI) */