board/myir/mys_6ulx/mys_6ulx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2020 Linumiz
   4  * Author: Parthiban Nallathambi <parthiban@linumiz.com>
   5  */
   6
   7 #include <init.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/crm_regs.h>
  10 #include <asm/arch/mx6-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/global_data.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <asm/mach-imx/mxc_i2c.h>
  15 #include <fsl_esdhc_imx.h>
  16 #include <linux/bitops.h>
  17 #include <miiphy.h>
  18 #include <netdev.h>
  19 #include <usb.h>
  20 #include <usb/ehci-ci.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 int dram_init(void)
  25 {
  26         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  27
  28         return 0;
  29 }
  30
  31 #define UART_PAD_CTRL  (PAD_CTL_PKE         | PAD_CTL_PUE       | \
  32                         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  33                         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | \
  34                         PAD_CTL_HYS)
  35
  36 static iomux_v3_cfg_t const uart1_pads[] = {
  37         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  38         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  39 };
  40
  41 static iomux_v3_cfg_t const uart5_pads[] = {
  42         MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  43         MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  44         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  45         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  46 };
  47
  48 static void setup_iomux_uart(void)
  49 {
  50         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  51         imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  52 }
  53
  54 #ifdef CONFIG_FEC_MXC
  55
  56 static int setup_fec(void)
  57 {
  58         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  59         int ret;
  60
  61         /*
  62          * Use 50M anatop loopback REF_CLK1 for ENET1,
  63          * clear gpr1[13], set gpr1[17].
  64          */
  65         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  66                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  67
  68         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  69         if (ret)
  70                 return ret;
  71
  72         enable_enet_clk(1);
  73
  74         return 0;
  75 }
  76
  77 int board_phy_config(struct phy_device *phydev)
  78 {
  79         /*
  80          * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
  81          * 50 MHz RMII clock mode.
  82          */
  83         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  84
  85         if (phydev->drv->config)
  86                 phydev->drv->config(phydev);
  87
  88         return 0;
  89 }
  90 #endif /* CONFIG_FEC_MXC */
  91
  92 int board_early_init_f(void)
  93 {
  94         setup_iomux_uart();
  95
  96         return 0;
  97 }
  98
  99 int board_init(void)
 100 {
 101         /* Address of boot parameters */
 102         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 103
 104 #ifdef CONFIG_FEC_MXC
 105         setup_fec();
 106 #endif
 107         return 0;
 108 }
 109
 110 int checkboard(void)
 111 {
 112         u32 cpurev = get_cpu_rev();
 113
 114         printf("Board: MYiR MYS-6ULX %s Single Board Computer\n",
 115                get_imx_type((cpurev & 0xFF000) >> 12));
 116
 117         return 0;
 118 }