2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
5 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #if defined(CONFIG_OF_LIBFDT)
34 DECLARE_GLOBAL_DATA_PTR;
36 /* System RAM mapped to PCI space */
37 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
38 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
42 void pci_mvblm7_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
44 unsigned char line = 0xff;
46 if (PCI_BUS(dev) == 0) {
47 switch (PCI_DEV(dev)) {
57 printf("***pci_scan: illegal dev = 0x%08x\n",
62 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
66 static struct pci_controller pci_hose = {
67 fixup_irq:pci_mvblm7_fixup_irq
70 int mvblm7_load_fpga(void)
73 void *fpga_data = NULL;
74 char *datastr = getenv("fpgadata");
75 char *sizestr = getenv("fpgadatasize");
78 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
80 data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
82 return fpga_load(0, fpga_data, data_size);
85 static struct pci_region pci_regions[] = {
87 bus_start: CFG_PCI1_MEM_BASE,
88 phys_start: CFG_PCI1_MEM_PHYS,
89 size: CFG_PCI1_MEM_SIZE,
90 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
93 bus_start: CFG_PCI1_MMIO_BASE,
94 phys_start: CFG_PCI1_MMIO_PHYS,
95 size: CFG_PCI1_MMIO_SIZE,
99 bus_start: CFG_PCI1_IO_BASE,
100 phys_start: CFG_PCI1_IO_PHYS,
101 size: CFG_PCI1_IO_SIZE,
106 void pci_init_board(void)
112 volatile immap_t *immr;
113 volatile pcictrl83xx_t *pci_ctrl;
114 volatile gpio83xx_t *gpio;
115 volatile clk83xx_t *clk;
116 volatile law83xx_t *pci_law;
117 struct pci_region *reg[] = { pci_regions };
120 immr = (immap_t *) CFG_IMMR;
121 clk = (clk83xx_t *) &immr->clk;
122 pci_ctrl = immr->pci_ctrl;
123 pci_law = immr->sysconf.pcilaw;
124 gpio = (volatile gpio83xx_t *)&immr->gpio[0];
126 s = getenv("skip_fpga");
128 printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
132 gpio->dat = MV_GPIO_DAT;
133 gpio->odr = MV_GPIO_ODE;
135 gpio->dir = MV_GPIO_OUT;
137 gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
139 printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
140 immr->sysconf.sicrl);
146 /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
147 clk->occr = 0xc0000000;
153 for (i = 0; i < 1000; ++i)
156 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
157 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
159 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
160 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
162 warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
164 mpc83xx_pci_init(1, reg, warmboot);