1 /* SPDX-License-Identifier: GPL-2.0+ */
4 Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
6 Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
8 Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
13 #include <asm/processor.h>
14 #include <asm/macro.h>
16 #ifdef CONFIG_CPU_SH7751
17 #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
18 #define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
19 #ifdef CONFIG_MARUBUN_PCCARD
20 #define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
21 A3:2 A2:15 A1:15 A0:6 A0B:7 */
22 #else /* CONFIG_MARUBUN_PCCARD */
23 #define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
24 A3:2 A2:15 A1:15 A0:6 A0B:7 */
25 #endif /* CONFIG_MARUBUN_PCCARD */
26 #define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
27 A2: 1-3 A1: 1-3 A0: 0-1 */
28 #define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
29 #define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
30 #define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
31 #define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
32 #else /* CONFIG_CPU_SH7751 */
33 #define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
34 #define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
35 #define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
36 A3:2 A2:15 A1:15 A0:15 A0B:7 */
37 #define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
38 A2: 1-3 A1: 1-3 A0: 0-1 */
39 #define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
40 #define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
41 #define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
42 #define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
43 #endif /* CONFIG_CPU_SH7751 */
51 write32 CCR_A, CCR_D_DISABLE
54 write16 FRQCR_A, FRQCR_D
56 write32 BCR1_A, BCR1_D
58 write16 BCR2_A, BCR2_D
60 write32 WCR1_A, WCR1_D
62 write32 WCR2_A, WCR2_D
64 write32 WCR3_A, WCR3_D
69 write8 SDMR3_A, SDMR3_D
71 ! Do you need PCMCIA setting?
72 ! If so, please add the lines here...
74 write16 RTCNT_A, RTCNT_D
76 write16 RTCOR_A, RTCOR_D
78 write16 RTCSR_A, RTCSR_D
80 write16 RFCR_A, RFCR_D
82 /* Wait DRAM refresh 30 times */
93 write8 SDMR3_A, SDMR3_D
101 CCR_D_DISABLE: .long 0x0808
104 #ifdef CONFIG_CPU_TYPE_R
105 .word 0x0e1a /* 12:3:3 */
106 #else /* CONFIG_CPU_TYPE_R */
107 #ifdef CONFIG_GOOD_SESH4
108 .word 0x00e13 /* 6:2:1 */
110 .word 0x00e23 /* 6:1:1 */
113 #endif /* CONFIG_CPU_TYPE_R */
116 BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
118 BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
120 WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
122 WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
124 WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
126 RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
129 RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
132 RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */
134 SDMR3_A: .long SDMR3_ADDRESS
137 MCR_D1: .long MCR_D1_VALUE
138 MCR_D2: .long MCR_D2_VALUE
140 RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */