3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 * Kenati Technologies, Inc.
8 * board/ms7722se/lowlevel_init.S
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
32 * Board specific low level init code, called _very_ early in the
33 * startup sequence. Relocation to SDRAM has not happened yet, no
34 * stack is available, bss section has not been initialised, etc.
36 * (Note: As no stack is available, no subroutines can be called...).
46 mov.l CCR_A, r1 ! Address of Cache Control Register
47 mov.l CCR_D, r0 ! Instruction Cache Invalidate
50 mov.l MMUCR_A, r1 ! Address of MMU Control Register
51 mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
54 mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
58 mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
70 ! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
71 ! mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
74 mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
75 mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
78 mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
79 mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
82 mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
86 mov.l CCR_A, r1 ! Address of Cache Control Register
87 mov.l CCR_D_2, r0 ! ??
116 mov.l CMNCR_A, r1 ! CMNCR address -> R1
117 mov.l CMNCR_D, r0 ! CMNCR data -> R0
118 mov.l r0, @r1 ! CMNCR set
120 mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
121 mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
122 mov.l r0, @r1 ! CS0BCR set
124 mov.l CS2BCR_A, r1 ! CS2BCR address -> R1
125 mov.l CS2BCR_D, r0 ! CS2BCR data -> R0
126 mov.l r0, @r1 ! CS2BCR set
128 mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
129 mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
130 mov.l r0, @r1 ! CS4BCR set
132 mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
133 mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
134 mov.l r0, @r1 ! CS5ABCR set
136 mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
137 mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
138 mov.l r0, @r1 ! CS5BBCR set
140 mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
141 mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
142 mov.l r0, @r1 ! CS6ABCR set
144 mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
145 mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
146 mov.l r0, @r1 ! CS0WCR set
148 mov.l CS2WCR_A, r1 ! CS2WCR address -> R1
149 mov.l CS2WCR_D, r0 ! CS2WCR data -> R0
150 mov.l r0, @r1 ! CS2WCR set
152 mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
153 mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
154 mov.l r0, @r1 ! CS4WCR set
156 mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
157 mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
158 mov.l r0, @r1 ! CS5AWCR set
160 mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
161 mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
162 mov.l r0, @r1 ! CS5BWCR set
164 mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
165 mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
166 mov.l r0, @r1 ! CS6AWCR set
168 ! SDRAM initialization
169 mov.l SDCR_A, r1 ! SB_SDCR address -> R1
170 mov.l SDCR_D, r0 ! SB_SDCR data -> R0
171 mov.l r0, @r1 ! SB_SDCR set
173 mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
174 mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
175 mov.l r0, @r1 ! SB_SDWCR set
177 mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
178 mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
179 mov.l r0, @r1 ! SB_SDPCR set
181 mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
182 mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
183 mov.l r0, @r1 ! SB_RTCOR set
185 mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
186 mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
187 mov.l r0, @r1 ! SB_RTCSR set
189 mov.l SDMR3_A, r1 ! SDMR3 address -> R1
190 mov #0x00, r0 ! SDMR3 data -> R0
191 mov.b r0, @r1 ! SDMR3 set
193 ! BL bit off (init = ON) (?!?)
195 stc sr, r0 ! BL bit off(init=ON)
207 MSTPCR0_A: .long MSTPCR0
208 MSTPCR2_A: .long MSTPCR2
211 RWTCSR_A: .long RWTCSR
212 RWTCNT_A: .long RWTCNT
215 CCR_D: .long 0x00000800
216 CCR_D_2: .long 0x00000103
217 MMUCR_D: .long 0x00000004
218 MSTPCR0_D: .long 0x00001001
219 MSTPCR2_D: .long 0xffffffff
220 FRQCR_D: .long 0x07022538
222 PSELA_A: .long 0xa405014E
223 PSELA_D: .word 0x0A10
226 DRVCR_A: .long 0xa405018A
227 DRVCR_D: .word 0x0554
230 PCCR_A: .long 0xa4050104
234 PECR_A: .long 0xa4050108
238 PJCR_A: .long 0xa4050110
242 PXCR_A: .long 0xa4050148
247 CMNCR_D: .long 0x00000013
248 CS0BCR_A: .long CS0BCR ! Flash bank 1
249 CS0BCR_D: .long 0x24920400
250 CS2BCR_A: .long CS2BCR ! SRAM
251 CS2BCR_D: .long 0x24920400
252 CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
253 CS4BCR_D: .long 0x24920400
254 CS5ABCR_A: .long CS5ABCR ! Ext slot
255 CS5ABCR_D: .long 0x24920400
256 CS5BBCR_A: .long CS5BBCR ! USB controller
257 CS5BBCR_D: .long 0x24920400
258 CS6ABCR_A: .long CS6ABCR ! Ethernet
259 CS6ABCR_D: .long 0x24920400
261 CS0WCR_A: .long CS0WCR
262 CS0WCR_D: .long 0x00000300
263 CS2WCR_A: .long CS2WCR
264 CS2WCR_D: .long 0x00000300
265 CS4WCR_A: .long CS4WCR
266 CS4WCR_D: .long 0x00000300
267 CS5AWCR_A: .long CS5AWCR
268 CS5AWCR_D: .long 0x00000300
269 CS5BWCR_A: .long CS5BWCR
270 CS5BWCR_D: .long 0x00000300
271 CS6AWCR_A: .long CS6AWCR
272 CS6AWCR_D: .long 0x00000300
274 SDCR_A: .long SBSC_SDCR
275 SDCR_D: .long 0x00020809
276 SDWCR_A: .long SBSC_SDWCR
277 SDWCR_D: .long 0x00164d0d
278 SDPCR_A: .long SBSC_SDPCR
279 SDPCR_D: .long 0x00000087
280 RTCOR_A: .long SBSC_RTCOR
281 RTCOR_D: .long 0xA55A0034
282 RTCSR_A: .long SBSC_RTCSR
283 RTCSR_D: .long 0xA55A0010
284 SDMR3_A: .long 0xFE500180
288 SBSCR_D: .word 0x0040
290 RWTCSR_D_1: .word 0xA507
291 RWTCSR_D_2: .word 0xA507
292 RWTCNT_D: .word 0x5A00
294 SR_MASK_D: .long 0xEFFFFF0F