2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
4 /*-----------------------------------------------------------------------------
5 * Function: ext_bus_cntlr_init
6 * Description: Initializes the External Bus Controller for the external
7 * peripherals. IMPORTANT: For pass1 this code must run from
8 * cache since you can not reliably change a peripheral banks
9 * timing register (pbxap) while running code from that bank.
10 * For ex., since we are running from ROM on bank 0, we can NOT
11 * execute the code that modifies bank 0 timings from ROM, so
12 * we run it from cache.
13 * Bank 0 - Flash or Multi Purpose Socket
14 * Bank 1 - Multi Purpose Socket or Flash
19 * Bank 6 - used to switch on the 12V for the Multipurpose socket
20 * Bank 7 - Config Register
21 *-----------------------------------------------------------------------------*/
23 #include <configs/PIP405.h>
24 #include <ppc_asm.tmpl>
27 #include <asm/cache.h>
29 #include <asm/ppc4xx.h>
32 .globl ext_bus_cntlr_init
34 mflr r4 /* save link register */
35 mfdcr r3,CPC0_PSR /* get strapping reg */
36 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
37 bnelr /* jump back if PCI boot */
41 mflr r3 /* get address of ..getAddr */
42 mtlr r4 /* restore link register */
43 addi r4,0,14 /* set ctr to 14; used to prefetch */
44 mtctr r4 /* 14 cache lines to fit this function */
45 /* in cache (gives us 8x14=112 instrctns) */
47 icbt r0,r3 /* prefetch cache line for addr in r3 */
48 addi r3,r3,32 /* move to next cache line */
49 bdnz ..ebcloop /* continue for 14 cache lines */
51 /*-------------------------------------------------------------------
52 * Delay to ensure all accesses to ROM are complete before changing
54 *------------------------------------------------------------------- */
59 bdnz ..spinlp /* spin loop */
61 /*-----------------------------------------------------------------------
63 *----------------------------------------------------------------------- */
68 andi. r0, r4, 0x2000 /* mask out irrelevant bits */
69 beq 0f /* jump if 8 bit bus width */
71 /* setup 16 bit things
72 *-----------------------------------------------------------------------
73 * Memory Bank 0 (16 Bit Flash) initialization
74 *---------------------------------------------------------------------- */
78 addis r4,0,(FLASH_AP_B)@h
79 ori r4,r4,(FLASH_AP_B)@l
84 /* BS=0x010(4MB),BU=0x3(R/W), */
85 addis r4,0,(FLASH_CR_B)@h
86 ori r4,r4,(FLASH_CR_B)@l
92 /*-----------------------------------------------------------------------
93 * Memory Bank 0 Multi Purpose Socket initialization
94 *----------------------------------------------------------------------- */
95 /* 0x7F8FFE80 slowest boot */
98 addis r4,0,(MPS_AP_B)@h
99 ori r4,r4,(MPS_AP_B)@l
100 mtdcr EBC0_CFGDATA,r4
103 mtdcr EBC0_CFGADDR,r4
104 /* BS=0x010(4MB),BU=0x3(R/W), */
105 addis r4,0,(MPS_CR_B)@h
106 ori r4,r4,(MPS_CR_B)@l
107 mtdcr EBC0_CFGDATA,r4
111 /*-----------------------------------------------------------------------
112 * Memory Bank 2-3-4-5-6 (not used) initialization
113 *-----------------------------------------------------------------------*/
115 mtdcr EBC0_CFGADDR,r4
118 mtdcr EBC0_CFGDATA,r4
121 mtdcr EBC0_CFGADDR,r4
124 mtdcr EBC0_CFGDATA,r4
127 mtdcr EBC0_CFGADDR,r4
130 mtdcr EBC0_CFGDATA,r4
133 mtdcr EBC0_CFGADDR,r4
136 mtdcr EBC0_CFGDATA,r4
139 mtdcr EBC0_CFGADDR,r4
142 mtdcr EBC0_CFGDATA,r4
145 mtdcr EBC0_CFGADDR,r4
148 mtdcr EBC0_CFGDATA,r4
151 mtdcr EBC0_CFGADDR,r4
154 mtdcr EBC0_CFGDATA,r4
155 nop /* pass2 DCR errata #8 */
158 #if defined(CONFIG_BOOT_PCI)
159 .section .bootpg,"ax"
161 /*******************************************
165 /* first handle errata #68 / PCI_18 */
166 iccci r0, r0 /* invalidate I-cache */
168 mticcr r31 /* ICCR = 0 (all uncachable) */
171 mfccr0 r28 /* set CCR0[24] = 1 */
175 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
177 addi r28, r28, 0x0004
178 stw r31, 0x0C(r28) /* clear PMM0PCIHA */
179 lis r29, 0xFFF8 /* open 512 kByte */
180 addi r29, r29, 0x0001/* and enable this region */
181 stwbrx r29, r0, r28 /* write PMM0MA */
183 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
184 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
186 lis r31, 0x8000 /* set en bit bus 0 */
187 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
188 stwbrx r31, r0, r28 /* write it */
190 lwbrx r31, r0, r29 /* load XBCS register */
191 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
192 stwbrx r31, r0, r29 /* write back XBCS register */
196 b _start /* normal start */