2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
5 * Adapted for PIP405 03.07.01
6 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
18 DECLARE_GLOBAL_DATA_PTR;
20 #include "piix4_pci.h"
21 #include "pci_parts.h"
23 void pci_405gp_init(struct pci_controller *hose);
25 void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
26 struct pci_config_table *entry)
28 struct pci_pip405_config_entry *table;
31 table = (struct pci_pip405_config_entry *)entry->priv[0];
33 for (i = 0; table[i].width; i++) {
35 printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
36 table[i].index, table[i].val, table[i].width);
39 switch (table[i].width) {
41 pci_hose_write_config_byte(hose, dev,
42 table[i].index, table[i].val);
45 pci_hose_write_config_word(hose, dev,
46 table[i].index, table[i].val);
49 pci_hose_write_config_dword(hose, dev,
50 table[i].index, table[i].val);
57 static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
59 unsigned char int_line = 0xff;
62 * Write pci interrupt line register
64 if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */
66 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
67 if ((pin == 0) || (pin > 4))
70 int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
71 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
73 printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
74 PCI_DEV(dev), dev, int_line, int_line);
79 static struct pci_controller hose = {
80 config_table: pci_pip405_config_table,
81 fixup_irq : pci_pip405_fixup_irq,
85 void pci_init_board(void)
87 /*we want the ptrs to RAM not flash (ie don't use init list)*/
88 hose.fixup_irq = pci_pip405_fixup_irq;
89 hose.config_table = pci_pip405_config_table;
91 printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",
92 pci_pip405_fixup_irq, pci_pip405_config_table, hose);
94 pci_405gp_init(&hose);
97 #endif /* CONFIG_PCI */
98 #endif /* CONFIG_405GP */