2 * Copyright 2004 Freescale Semiconductor.
3 * Jeff Brown (jeffrey@freescale.com)
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_86xx.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
36 extern void ft_cpu_setup(void *blob, bd_t *bd);
42 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
43 extern void ddr_enable_ecc(unsigned int dram_size);
46 extern long int spd_sdram(void);
48 void sdram_init(void);
49 long int fixed_sdram(void);
52 int board_early_init_f (void)
59 puts("Board: MPC8641HPCN\n");
63 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
64 volatile ccsr_gur_t *gur = &immap->im_gur;
65 volatile ccsr_pex_t *pex1 = &immap->im_pex1;
67 uint devdisr = gur->devdisr;
68 uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
69 uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
70 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
73 if ((io_sel==2 || io_sel==3 || io_sel==5 \
74 || io_sel==6 || io_sel==7 || io_sel==0xF)
75 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
76 debug ("PCI-EXPRESS 1: %s \n",
77 pex1_agent ? "Agent" : "Host");
78 debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
79 if (pex1->pme_msg_det) {
80 pex1->pme_msg_det = 0xffffffff;
81 debug (" with errors. Clearing. Now 0x%08x",
86 printf ("PCI-EXPRESS 1: Disabled\n");
90 printf("PCI-EXPRESS1: Disabled\n");
98 initdram(int board_type)
101 extern long spd_sdram (void);
103 #if defined(CONFIG_SPD_EEPROM)
104 dram_size = spd_sdram ();
106 dram_size = fixed_sdram ();
109 #if defined(CFG_RAMBOOT)
114 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
116 * Initialize and enable DDR ECC.
118 ddr_enable_ecc(dram_size);
126 #if defined(CFG_DRAM_TEST)
129 uint *pstart = (uint *) CFG_MEMTEST_START;
130 uint *pend = (uint *) CFG_MEMTEST_END;
133 printf("SDRAM test phase 1:\n");
134 for (p = pstart; p < pend; p++)
137 for (p = pstart; p < pend; p++) {
138 if (*p != 0xaaaaaaaa) {
139 printf ("SDRAM test fails at: %08x\n", (uint) p);
144 printf("SDRAM test phase 2:\n");
145 for (p = pstart; p < pend; p++)
148 for (p = pstart; p < pend; p++) {
149 if (*p != 0x55555555) {
150 printf ("SDRAM test fails at: %08x\n", (uint) p);
155 printf("SDRAM test passed.\n");
161 #if !defined(CONFIG_SPD_EEPROM)
163 * Fixed sdram init -- doesn't use serial presence detect.
165 long int fixed_sdram(void)
167 #if !defined(CFG_RAMBOOT)
168 volatile immap_t *immap = (immap_t *)CFG_IMMR;
169 volatile ccsr_ddr_t *ddr= &immap->im_ddr1;
171 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
172 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
173 ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
174 ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
175 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
176 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
177 ddr->sdram_mode_1 = CFG_DDR_MODE_1;
178 ddr->sdram_mode_2 = CFG_DDR_MODE_2;
179 ddr->sdram_interval = CFG_DDR_INTERVAL;
180 ddr->sdram_data_init = CFG_DDR_DATA_INIT;
181 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
182 ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
183 ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
185 #if defined (CONFIG_DDR_ECC)
186 ddr->err_disable = 0x0000008D;
187 ddr->err_sbe = 0x00ff0000;
193 #if defined (CONFIG_DDR_ECC)
194 /* Enable ECC checking */
195 ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
197 ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
198 ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
204 return CFG_SDRAM_SIZE * 1024 * 1024;
206 #endif /* !defined(CONFIG_SPD_EEPROM) */
209 #if defined(CONFIG_PCI)
211 * Initialize PCI Devices, report devices found.
214 #ifndef CONFIG_PCI_PNP
215 static struct pci_config_table pci_fsl86xxads_config_table[] = {
216 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
217 PCI_IDSEL_NUMBER, PCI_ANY_ID,
218 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
220 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
227 static struct pci_controller hose = {
228 #ifndef CONFIG_PCI_PNP
229 config_table: pci_mpc86xxcts_config_table,
233 #endif /* CONFIG_PCI */
240 extern void pci_mpc86xx_init(struct pci_controller *hose);
242 pci_mpc86xx_init(&hose);
243 #endif /* CONFIG_PCI */
246 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
248 ft_board_setup(void *blob, bd_t *bd)
253 ft_cpu_setup(blob, bd);
255 p = ft_get_prop(blob, "/memory/reg", &len);
257 *p++ = cpu_to_be32(bd->bi_memstart);
258 *p = cpu_to_be32(bd->bi_memsize);
266 mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
275 case 'f': /* reset with frequency changed */
278 read_from_px_regs(0);
280 val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
282 corepll = strfractoint(argv[3]);
283 val = val + set_px_corepll(corepll);
284 val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
286 printf("Setting registers VCFGEN0 and VCTL\n");
287 read_from_px_regs(1);
288 printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
293 while (1); /* Not reached */
296 if (argv[2][1] == 'f') {
297 read_from_px_regs(0);
298 read_from_px_regs_altbank(0);
299 /* reset with frequency changed */
300 val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
302 corepll = strfractoint(argv[4]);
303 val = val + set_px_corepll(corepll);
304 val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10));
306 printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
308 read_from_px_regs(1);
309 read_from_px_regs_altbank(1);
310 printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
311 set_px_go_with_watchdog();
315 while(1); /* Not reached */
317 } else if(argv[2][1] == 'd'){
318 /* Reset from next bank without changing frequencies but with watchdog timer enabled */
319 read_from_px_regs(0);
320 read_from_px_regs_altbank(0);
321 printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
323 read_from_px_regs_altbank(1);
324 printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
325 set_px_go_with_watchdog();
326 while(1); /* Not reached */
329 /* Reset from next bank without changing frequency and without watchdog timer enabled */
330 read_from_px_regs(0);
331 read_from_px_regs_altbank(0);
334 printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
336 read_from_px_regs_altbank(1);
337 printf("Resetting board to boot from the other bank....\n");
346 printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
347 printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
348 printf("For example: reset cf 40 2.5 10\n");
349 printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
353 out8(PIXIS_BASE+PIXIS_RST,0);