2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
34 #if defined(CONFIG_DDR_ECC)
35 extern void ddr_enable_ecc(unsigned int dram_size);
38 extern long int spd_sdram(void);
40 void local_bus_init(void);
41 void sdram_init(void);
42 long int fixed_sdram(void);
45 int board_early_init_f (void)
47 #if defined(CONFIG_PCI)
48 volatile immap_t *immr = (immap_t *)CFG_IMMR;
49 volatile ccsr_pcix_t *pci = &immr->im_pcix;
51 pci->peer &= 0xffffffdf; /* disable master abort */
62 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
63 CONFIG_SYS_CLK_FREQ / 1000000);
65 printf(" PCI1: disabled\n");
69 * Initialize local bus.
78 initdram(int board_type)
81 extern long spd_sdram (void);
82 volatile immap_t *immap = (immap_t *)CFG_IMMR;
84 puts("Initializing\n");
86 #if defined(CONFIG_DDR_DLL)
88 volatile ccsr_gur_t *gur= &immap->im_gur;
92 * Work around to stabilize DDR DLL
94 temp_ddrdll = gur->ddrdllcr;
95 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
96 asm("sync;isync;msync");
100 #if defined(CONFIG_SPD_EEPROM)
101 dram_size = spd_sdram ();
103 dram_size = fixed_sdram ();
106 #if defined(CONFIG_DDR_ECC)
108 * Initialize and enable DDR ECC.
110 ddr_enable_ecc(dram_size);
124 * Initialize Local Bus
130 volatile immap_t *immap = (immap_t *)CFG_IMMR;
131 volatile ccsr_gur_t *gur = &immap->im_gur;
132 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
140 * Fix Local Bus clock glitch when DLL is enabled.
142 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
143 * If localbus freq is > 133Mhz, DLL can be safely enabled.
144 * Between 66 and 133, the DLL is enabled with an override workaround.
147 get_sys_info(&sysinfo);
148 clkdiv = lbc->lcrr & 0x0f;
149 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
152 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
154 } else if (lbc_hz >= 133) {
155 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
159 * On REV1 boards, need to change CLKDIV before enable DLL.
160 * Default CLKDIV is 8, change it to 4 temporarily.
162 uint pvr = get_pvr();
163 uint temp_lbcdll = 0;
165 if (pvr == PVR_85xx_REV1) {
166 /* FIXME: Justify the high bit here. */
167 lbc->lcrr = 0x10000004;
170 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
174 * Sample LBC DLL ctrl reg, upshift it to set the
177 temp_lbcdll = gur->lbcdllcr;
178 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
179 asm("sync;isync;msync");
185 * Initialize SDRAM memory on the Local Bus.
191 volatile immap_t *immap = (immap_t *)CFG_IMMR;
192 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
193 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
196 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
199 * Setup SDRAM Base and Option Registers
201 lbc->or2 = CFG_OR2_PRELIM;
202 lbc->br2 = CFG_BR2_PRELIM;
203 lbc->lbcr = CFG_LBC_LBCR;
206 lbc->lsrt = CFG_LBC_LSRT;
207 lbc->mrtpr = CFG_LBC_MRTPR;
211 * Configure the SDRAM controller.
213 lbc->lsdmr = CFG_LBC_LSDMR_1;
216 ppcDcbf((unsigned long) sdram_addr);
219 lbc->lsdmr = CFG_LBC_LSDMR_2;
222 ppcDcbf((unsigned long) sdram_addr);
225 lbc->lsdmr = CFG_LBC_LSDMR_3;
228 ppcDcbf((unsigned long) sdram_addr);
231 lbc->lsdmr = CFG_LBC_LSDMR_4;
234 ppcDcbf((unsigned long) sdram_addr);
237 lbc->lsdmr = CFG_LBC_LSDMR_5;
240 ppcDcbf((unsigned long) sdram_addr);
245 #if defined(CFG_DRAM_TEST)
248 uint *pstart = (uint *) CFG_MEMTEST_START;
249 uint *pend = (uint *) CFG_MEMTEST_END;
252 printf("SDRAM test phase 1:\n");
253 for (p = pstart; p < pend; p++)
256 for (p = pstart; p < pend; p++) {
257 if (*p != 0xaaaaaaaa) {
258 printf ("SDRAM test fails at: %08x\n", (uint) p);
263 printf("SDRAM test phase 2:\n");
264 for (p = pstart; p < pend; p++)
267 for (p = pstart; p < pend; p++) {
268 if (*p != 0x55555555) {
269 printf ("SDRAM test fails at: %08x\n", (uint) p);
274 printf("SDRAM test passed.\n");
280 #if !defined(CONFIG_SPD_EEPROM)
281 /*************************************************************************
282 * fixed sdram init -- doesn't use serial presence detect.
283 ************************************************************************/
284 long int fixed_sdram (void)
287 volatile immap_t *immap = (immap_t *)CFG_IMMR;
288 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
290 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
291 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
292 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
293 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
294 ddr->sdram_mode = CFG_DDR_MODE;
295 ddr->sdram_interval = CFG_DDR_INTERVAL;
296 #if defined (CONFIG_DDR_ECC)
297 ddr->err_disable = 0x0000000D;
298 ddr->err_sbe = 0x00ff0000;
300 asm("sync;isync;msync");
302 #if defined (CONFIG_DDR_ECC)
303 /* Enable ECC checking */
304 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
306 ddr->sdram_cfg = CFG_DDR_CONTROL;
308 asm("sync; isync; msync");
311 return CFG_SDRAM_SIZE * 1024 * 1024;
313 #endif /* !defined(CONFIG_SPD_EEPROM) */
316 #if defined(CONFIG_PCI)
318 * Initialize PCI Devices, report devices found.
321 #ifndef CONFIG_PCI_PNP
322 static struct pci_config_table pci_mpc85xxads_config_table[] = {
323 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
324 PCI_IDSEL_NUMBER, PCI_ANY_ID,
325 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
327 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
334 static struct pci_controller hose = {
335 #ifndef CONFIG_PCI_PNP
336 config_table: pci_mpc85xxads_config_table,
340 #endif /* CONFIG_PCI */
347 extern void pci_mpc85xx_init(struct pci_controller *hose);
349 pci_mpc85xx_init(&hose);
350 #endif /* CONFIG_PCI */