board/mpc8360emds/mpc8360emds.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  * based on board/mpc8349emds/mpc8349emds.c
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  */
  15
  16 #include <common.h>
  17 #include <ioports.h>
  18 #include <mpc83xx.h>
  19 #include <i2c.h>
  20 #include <spd.h>
  21 #include <miiphy.h>
  22 #include <command.h>
  23 #if defined(CONFIG_PCI)
  24 #include <pci.h>
  25 #endif
  26 #if defined(CONFIG_SPD_EEPROM)
  27 #include <spd_sdram.h>
  28 #else
  29 #include <asm/mmu.h>
  30 #endif
  31 #if defined(CONFIG_OF_FLAT_TREE)
  32 #include <ft_build.h>
  33 #endif
  34
  35 const qe_iop_conf_t qe_iop_conf_tab[] = {
  36         /* GETH1 */
  37         {0,  3, 1, 0, 1}, /* TxD0 */
  38         {0,  4, 1, 0, 1}, /* TxD1 */
  39         {0,  5, 1, 0, 1}, /* TxD2 */
  40         {0,  6, 1, 0, 1}, /* TxD3 */
  41         {1,  6, 1, 0, 3}, /* TxD4 */
  42         {1,  7, 1, 0, 1}, /* TxD5 */
  43         {1,  9, 1, 0, 2}, /* TxD6 */
  44         {1, 10, 1, 0, 2}, /* TxD7 */
  45         {0,  9, 2, 0, 1}, /* RxD0 */
  46         {0, 10, 2, 0, 1}, /* RxD1 */
  47         {0, 11, 2, 0, 1}, /* RxD2 */
  48         {0, 12, 2, 0, 1}, /* RxD3 */
  49         {0, 13, 2, 0, 1}, /* RxD4 */
  50         {1,  1, 2, 0, 2}, /* RxD5 */
  51         {1,  0, 2, 0, 2}, /* RxD6 */
  52         {1,  4, 2, 0, 2}, /* RxD7 */
  53         {0,  7, 1, 0, 1}, /* TX_EN */
  54         {0,  8, 1, 0, 1}, /* TX_ER */
  55         {0, 15, 2, 0, 1}, /* RX_DV */
  56         {0, 16, 2, 0, 1}, /* RX_ER */
  57         {0,  0, 2, 0, 1}, /* RX_CLK */
  58         {2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
  59         {2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
  60         /* GETH2 */
  61         {0, 17, 1, 0, 1}, /* TxD0 */
  62         {0, 18, 1, 0, 1}, /* TxD1 */
  63         {0, 19, 1, 0, 1}, /* TxD2 */
  64         {0, 20, 1, 0, 1}, /* TxD3 */
  65         {1,  2, 1, 0, 1}, /* TxD4 */
  66         {1,  3, 1, 0, 2}, /* TxD5 */
  67         {1,  5, 1, 0, 3}, /* TxD6 */
  68         {1,  8, 1, 0, 3}, /* TxD7 */
  69         {0, 23, 2, 0, 1}, /* RxD0 */
  70         {0, 24, 2, 0, 1}, /* RxD1 */
  71         {0, 25, 2, 0, 1}, /* RxD2 */
  72         {0, 26, 2, 0, 1}, /* RxD3 */
  73         {0, 27, 2, 0, 1}, /* RxD4 */
  74         {1, 12, 2, 0, 2}, /* RxD5 */
  75         {1, 13, 2, 0, 3}, /* RxD6 */
  76         {1, 11, 2, 0, 2}, /* RxD7 */
  77         {0, 21, 1, 0, 1}, /* TX_EN */
  78         {0, 22, 1, 0, 1}, /* TX_ER */
  79         {0, 29, 2, 0, 1}, /* RX_DV */
  80         {0, 30, 2, 0, 1}, /* RX_ER */
  81         {0, 31, 2, 0, 1}, /* RX_CLK */
  82         {2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
  83         {2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
  84
  85         {0,  1, 3, 0, 2}, /* MDIO */
  86         {0,  2, 1, 0, 1}, /* MDC */
  87
  88         {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  89 };
  90
  91 int board_early_init_f(void)
  92 {
  93
  94         u8 *bcsr = (u8 *)CFG_BCSR;
  95         const immap_t *immr = (immap_t *)CFG_IMMR;
  96
  97         /* Enable flash write */
  98         bcsr[0xa] &= ~0x04;
  99
 100         /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
 101         if (immr->sysconf.spridr == SPR_8360_REV20 ||
 102             immr->sysconf.spridr == SPR_8360E_REV20)
 103                 bcsr[0xe] = 0x30;
 104
 105         return 0;
 106 }
 107
 108 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 109 extern void ddr_enable_ecc(unsigned int dram_size);
 110 #endif
 111 int fixed_sdram(void);
 112 void sdram_init(void);
 113
 114 long int initdram(int board_type)
 115 {
 116         volatile immap_t *im = (immap_t *) CFG_IMMR;
 117         u32 msize = 0;
 118
 119         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 120                 return -1;
 121
 122         /* DDR SDRAM - Main SODIMM */
 123         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
 124 #if defined(CONFIG_SPD_EEPROM)
 125         msize = spd_sdram();
 126 #else
 127         msize = fixed_sdram();
 128 #endif
 129
 130 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 131         /*
 132          * Initialize DDR ECC byte
 133          */
 134         ddr_enable_ecc(msize * 1024 * 1024);
 135 #endif
 136         /*
 137          * Initialize SDRAM if it is on local bus.
 138          */
 139         sdram_init();
 140         puts("   DDR RAM: ");
 141         /* return total bus SDRAM size(bytes)  -- DDR */
 142         return (msize * 1024 * 1024);
 143 }
 144
 145 #if !defined(CONFIG_SPD_EEPROM)
 146 /*************************************************************************
 147  *  fixed sdram init -- doesn't use serial presence detect.
 148  ************************************************************************/
 149 int fixed_sdram(void)
 150 {
 151         volatile immap_t *im = (immap_t *) CFG_IMMR;
 152         u32 msize = 0;
 153         u32 ddr_size;
 154         u32 ddr_size_log2;
 155
 156         msize = CFG_DDR_SIZE;
 157         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 158              (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 159                 if (ddr_size & 1) {
 160                         return -1;
 161                 }
 162         }
 163         im->sysconf.ddrlaw[0].ar =
 164             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 165 #if (CFG_DDR_SIZE != 256)
 166 #warning Currenly any ddr size other than 256 is not supported
 167 #endif
 168 #ifdef CONFIG_DDR_II
 169         im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
 170         im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
 171         im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
 172         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 173         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 174         im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
 175         im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
 176         im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
 177         im->ddr.sdram_mode = CFG_DDR_MODE;
 178         im->ddr.sdram_mode2 = CFG_DDR_MODE2;
 179         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 180         im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
 181 #else
 182         im->ddr.csbnds[0].csbnds = 0x00000007;
 183         im->ddr.csbnds[1].csbnds = 0x0008000f;
 184
 185         im->ddr.cs_config[0] = CFG_DDR_CONFIG;
 186         im->ddr.cs_config[1] = CFG_DDR_CONFIG;
 187
 188         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 189         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 190         im->ddr.sdram_cfg = CFG_DDR_CONTROL;
 191
 192         im->ddr.sdram_mode = CFG_DDR_MODE;
 193         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 194 #endif
 195         udelay(200);
 196         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 197
 198         return msize;
 199 }
 200 #endif                          /*!CFG_SPD_EEPROM */
 201
 202 int checkboard(void)
 203 {
 204         puts("Board: Freescale MPC8360EMDS\n");
 205         return 0;
 206 }
 207
 208 /*
 209  * if MPC8360EMDS is soldered with SDRAM
 210  */
 211 #if defined(CFG_BR2_PRELIM)  \
 212         && defined(CFG_OR2_PRELIM) \
 213         && defined(CFG_LBLAWBAR2_PRELIM) \
 214         && defined(CFG_LBLAWAR2_PRELIM)
 215 /*
 216  * Initialize SDRAM memory on the Local Bus.
 217  */
 218
 219 void sdram_init(void)
 220 {
 221         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 222         volatile lbus83xx_t *lbc = &immap->lbus;
 223         uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
 224
 225         puts("\n   SDRAM on Local Bus: ");
 226         print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 227         /*
 228          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 229          */
 230         /*setup mtrpt, lsrt and lbcr for LB bus */
 231         lbc->lbcr = CFG_LBC_LBCR;
 232         lbc->mrtpr = CFG_LBC_MRTPR;
 233         lbc->lsrt = CFG_LBC_LSRT;
 234         asm("sync");
 235
 236         /*
 237          * Configure the SDRAM controller Machine Mode Register.
 238          */
 239         lbc->lsdmr = CFG_LBC_LSDMR_5;   /* Normal Operation */
 240         lbc->lsdmr = CFG_LBC_LSDMR_1;   /* Precharge All Banks */
 241         asm("sync");
 242         *sdram_addr = 0xff;
 243         udelay(100);
 244
 245         /*
 246          * We need do 8 times auto refresh operation.
 247          */
 248         lbc->lsdmr = CFG_LBC_LSDMR_2;
 249         asm("sync");
 250         *sdram_addr = 0xff;     /* 1 times */
 251         udelay(100);
 252         *sdram_addr = 0xff;     /* 2 times */
 253         udelay(100);
 254         *sdram_addr = 0xff;     /* 3 times */
 255         udelay(100);
 256         *sdram_addr = 0xff;     /* 4 times */
 257         udelay(100);
 258         *sdram_addr = 0xff;     /* 5 times */
 259         udelay(100);
 260         *sdram_addr = 0xff;     /* 6 times */
 261         udelay(100);
 262         *sdram_addr = 0xff;     /* 7 times */
 263         udelay(100);
 264         *sdram_addr = 0xff;     /* 8 times */
 265         udelay(100);
 266
 267         /* Mode register write operation */
 268         lbc->lsdmr = CFG_LBC_LSDMR_4;
 269         asm("sync");
 270         *(sdram_addr + 0xcc) = 0xff;
 271         udelay(100);
 272
 273         /* Normal operation */
 274         lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
 275         asm("sync");
 276         *sdram_addr = 0xff;
 277         udelay(100);
 278 }
 279 #else
 280 void sdram_init(void)
 281 {
 282         puts("SDRAM on Local Bus is NOT available!\n");
 283 }
 284 #endif
 285
 286 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 287 /*
 288  * ECC user commands
 289  */
 290 void ecc_print_status(void)
 291 {
 292         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 293         volatile ddr83xx_t *ddr = &immap->ddr;
 294
 295         printf("\nECC mode: %s\n\n",
 296                (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
 297
 298         /* Interrupts */
 299         printf("Memory Error Interrupt Enable:\n");
 300         printf("  Multiple-Bit Error Interrupt Enable: %d\n",
 301                (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
 302         printf("  Single-Bit Error Interrupt Enable: %d\n",
 303                (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
 304         printf("  Memory Select Error Interrupt Enable: %d\n\n",
 305                (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
 306
 307         /* Error disable */
 308         printf("Memory Error Disable:\n");
 309         printf("  Multiple-Bit Error Disable: %d\n",
 310                (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
 311         printf("  Sinle-Bit Error Disable: %d\n",
 312                (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
 313         printf("  Memory Select Error Disable: %d\n\n",
 314                (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
 315
 316         /* Error injection */
 317         printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
 318                ddr->data_err_inject_hi, ddr->data_err_inject_lo);
 319
 320         printf("Memory Data Path Error Injection Mask ECC:\n");
 321         printf("  ECC Mirror Byte: %d\n",
 322                (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
 323         printf("  ECC Injection Enable: %d\n",
 324                (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
 325         printf("  ECC Error Injection Mask: 0x%02x\n\n",
 326                ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
 327
 328         /* SBE counter/threshold */
 329         printf("Memory Single-Bit Error Management (0..255):\n");
 330         printf("  Single-Bit Error Threshold: %d\n",
 331                (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
 332         printf("  Single-Bit Error Counter: %d\n\n",
 333                (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
 334
 335         /* Error detect */
 336         printf("Memory Error Detect:\n");
 337         printf("  Multiple Memory Errors: %d\n",
 338                (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
 339         printf("  Multiple-Bit Error: %d\n",
 340                (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
 341         printf("  Single-Bit Error: %d\n",
 342                (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
 343         printf("  Memory Select Error: %d\n\n",
 344                (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
 345
 346         /* Capture data */
 347         printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
 348         printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
 349                ddr->capture_data_hi, ddr->capture_data_lo);
 350         printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
 351                ddr->capture_ecc & CAPTURE_ECC_ECE);
 352
 353         printf("Memory Error Attributes Capture:\n");
 354         printf(" Data Beat Number: %d\n",
 355                (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
 356                ECC_CAPT_ATTR_BNUM_SHIFT);
 357         printf("  Transaction Size: %d\n",
 358                (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
 359                ECC_CAPT_ATTR_TSIZ_SHIFT);
 360         printf("  Transaction Source: %d\n",
 361                (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
 362                ECC_CAPT_ATTR_TSRC_SHIFT);
 363         printf("  Transaction Type: %d\n",
 364                (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
 365                ECC_CAPT_ATTR_TTYP_SHIFT);
 366         printf("  Error Information Valid: %d\n\n",
 367                ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
 368 }
 369
 370 int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 371 {
 372         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 373         volatile ddr83xx_t *ddr = &immap->ddr;
 374         volatile u32 val;
 375         u64 *addr;
 376         u32 count;
 377         register u64 *i;
 378         u32 ret[2];
 379         u32 pattern[2];
 380         u32 writeback[2];
 381
 382         /* The pattern is written into memory to generate error */
 383         pattern[0] = 0xfedcba98UL;
 384         pattern[1] = 0x76543210UL;
 385
 386         /* After injecting error, re-initialize the memory with the value */
 387         writeback[0] = 0x01234567UL;
 388         writeback[1] = 0x89abcdefUL;
 389
 390         if (argc > 4) {
 391                 printf("Usage:\n%s\n", cmdtp->usage);
 392                 return 1;
 393         }
 394
 395         if (argc == 2) {
 396                 if (strcmp(argv[1], "status") == 0) {
 397                         ecc_print_status();
 398                         return 0;
 399                 } else if (strcmp(argv[1], "captureclear") == 0) {
 400                         ddr->capture_address = 0;
 401                         ddr->capture_data_hi = 0;
 402                         ddr->capture_data_lo = 0;
 403                         ddr->capture_ecc = 0;
 404                         ddr->capture_attributes = 0;
 405                         return 0;
 406                 }
 407         }
 408         if (argc == 3) {
 409                 if (strcmp(argv[1], "sbecnt") == 0) {
 410                         val = simple_strtoul(argv[2], NULL, 10);
 411                         if (val > 255) {
 412                                 printf("Incorrect Counter value, "
 413                                        "should be 0..255\n");
 414                                 return 1;
 415                         }
 416
 417                         val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
 418                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
 419
 420                         ddr->err_sbe = val;
 421                         return 0;
 422                 } else if (strcmp(argv[1], "sbethr") == 0) {
 423                         val = simple_strtoul(argv[2], NULL, 10);
 424                         if (val > 255) {
 425                                 printf("Incorrect Counter value, "
 426                                        "should be 0..255\n");
 427                                 return 1;
 428                         }
 429
 430                         val = (val << ECC_ERROR_MAN_SBET_SHIFT);
 431                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
 432
 433                         ddr->err_sbe = val;
 434                         return 0;
 435                 } else if (strcmp(argv[1], "errdisable") == 0) {
 436                         val = ddr->err_disable;
 437
 438                         if (strcmp(argv[2], "+sbe") == 0) {
 439                                 val |= ECC_ERROR_DISABLE_SBED;
 440                         } else if (strcmp(argv[2], "+mbe") == 0) {
 441                                 val |= ECC_ERROR_DISABLE_MBED;
 442                         } else if (strcmp(argv[2], "+mse") == 0) {
 443                                 val |= ECC_ERROR_DISABLE_MSED;
 444                         } else if (strcmp(argv[2], "+all") == 0) {
 445                                 val |= (ECC_ERROR_DISABLE_SBED |
 446                                         ECC_ERROR_DISABLE_MBED |
 447                                         ECC_ERROR_DISABLE_MSED);
 448                         } else if (strcmp(argv[2], "-sbe") == 0) {
 449                                 val &= ~ECC_ERROR_DISABLE_SBED;
 450                         } else if (strcmp(argv[2], "-mbe") == 0) {
 451                                 val &= ~ECC_ERROR_DISABLE_MBED;
 452                         } else if (strcmp(argv[2], "-mse") == 0) {
 453                                 val &= ~ECC_ERROR_DISABLE_MSED;
 454                         } else if (strcmp(argv[2], "-all") == 0) {
 455                                 val &= ~(ECC_ERROR_DISABLE_SBED |
 456                                          ECC_ERROR_DISABLE_MBED |
 457                                          ECC_ERROR_DISABLE_MSED);
 458                         } else {
 459                                 printf("Incorrect err_disable field\n");
 460                                 return 1;
 461                         }
 462
 463                         ddr->err_disable = val;
 464                         __asm__ __volatile__("sync");
 465                         __asm__ __volatile__("isync");
 466                         return 0;
 467                 } else if (strcmp(argv[1], "errdetectclr") == 0) {
 468                         val = ddr->err_detect;
 469
 470                         if (strcmp(argv[2], "mme") == 0) {
 471                                 val |= ECC_ERROR_DETECT_MME;
 472                         } else if (strcmp(argv[2], "sbe") == 0) {
 473                                 val |= ECC_ERROR_DETECT_SBE;
 474                         } else if (strcmp(argv[2], "mbe") == 0) {
 475                                 val |= ECC_ERROR_DETECT_MBE;
 476                         } else if (strcmp(argv[2], "mse") == 0) {
 477                                 val |= ECC_ERROR_DETECT_MSE;
 478                         } else if (strcmp(argv[2], "all") == 0) {
 479                                 val |= (ECC_ERROR_DETECT_MME |
 480                                         ECC_ERROR_DETECT_MBE |
 481                                         ECC_ERROR_DETECT_SBE |
 482                                         ECC_ERROR_DETECT_MSE);
 483                         } else {
 484                                 printf("Incorrect err_detect field\n");
 485                                 return 1;
 486                         }
 487
 488                         ddr->err_detect = val;
 489                         return 0;
 490                 } else if (strcmp(argv[1], "injectdatahi") == 0) {
 491                         val = simple_strtoul(argv[2], NULL, 16);
 492
 493                         ddr->data_err_inject_hi = val;
 494                         return 0;
 495                 } else if (strcmp(argv[1], "injectdatalo") == 0) {
 496                         val = simple_strtoul(argv[2], NULL, 16);
 497
 498                         ddr->data_err_inject_lo = val;
 499                         return 0;
 500                 } else if (strcmp(argv[1], "injectecc") == 0) {
 501                         val = simple_strtoul(argv[2], NULL, 16);
 502                         if (val > 0xff) {
 503                                 printf("Incorrect ECC inject mask, "
 504                                        "should be 0x00..0xff\n");
 505                                 return 1;
 506                         }
 507                         val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
 508
 509                         ddr->ecc_err_inject = val;
 510                         return 0;
 511                 } else if (strcmp(argv[1], "inject") == 0) {
 512                         val = ddr->ecc_err_inject;
 513
 514                         if (strcmp(argv[2], "en") == 0)
 515                                 val |= ECC_ERR_INJECT_EIEN;
 516                         else if (strcmp(argv[2], "dis") == 0)
 517                                 val &= ~ECC_ERR_INJECT_EIEN;
 518                         else
 519                                 printf("Incorrect command\n");
 520
 521                         ddr->ecc_err_inject = val;
 522                         __asm__ __volatile__("sync");
 523                         __asm__ __volatile__("isync");
 524                         return 0;
 525                 } else if (strcmp(argv[1], "mirror") == 0) {
 526                         val = ddr->ecc_err_inject;
 527
 528                         if (strcmp(argv[2], "en") == 0)
 529                                 val |= ECC_ERR_INJECT_EMB;
 530                         else if (strcmp(argv[2], "dis") == 0)
 531                                 val &= ~ECC_ERR_INJECT_EMB;
 532                         else
 533                                 printf("Incorrect command\n");
 534
 535                         ddr->ecc_err_inject = val;
 536                         return 0;
 537                 }
 538         }
 539         if (argc == 4) {
 540                 if (strcmp(argv[1], "testdw") == 0) {
 541                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 542                         count = simple_strtoul(argv[3], NULL, 16);
 543
 544                         if ((u32) addr % 8) {
 545                                 printf("Address not alligned on "
 546                                        "double word boundary\n");
 547                                 return 1;
 548                         }
 549                         disable_interrupts();
 550
 551                         for (i = addr; i < addr + count; i++) {
 552
 553                                 /* enable injects */
 554                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 555                                 __asm__ __volatile__("sync");
 556                                 __asm__ __volatile__("isync");
 557
 558                                 /* write memory location injecting errors */
 559                                 ppcDWstore((u32 *) i, pattern);
 560                                 __asm__ __volatile__("sync");
 561
 562                                 /* disable injects */
 563                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 564                                 __asm__ __volatile__("sync");
 565                                 __asm__ __volatile__("isync");
 566
 567                                 /* read data, this generates ECC error */
 568                                 ppcDWload((u32 *) i, ret);
 569                                 __asm__ __volatile__("sync");
 570
 571                                 /* re-initialize memory, double word write the location again,
 572                                  * generates new ECC code this time */
 573                                 ppcDWstore((u32 *) i, writeback);
 574                                 __asm__ __volatile__("sync");
 575                         }
 576                         enable_interrupts();
 577                         return 0;
 578                 }
 579                 if (strcmp(argv[1], "testword") == 0) {
 580                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 581                         count = simple_strtoul(argv[3], NULL, 16);
 582
 583                         if ((u32) addr % 8) {
 584                                 printf("Address not alligned on "
 585                                        "double word boundary\n");
 586                                 return 1;
 587                         }
 588                         disable_interrupts();
 589
 590                         for (i = addr; i < addr + count; i++) {
 591
 592                                 /* enable injects */
 593                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 594                                 __asm__ __volatile__("sync");
 595                                 __asm__ __volatile__("isync");
 596
 597                                 /* write memory location injecting errors */
 598                                 *(u32 *) i = 0xfedcba98UL;
 599                                 __asm__ __volatile__("sync");
 600
 601                                 /* sub double word write,
 602                                  * bus will read-modify-write,
 603                                  * generates ECC error */
 604                                 *((u32 *) i + 1) = 0x76543210UL;
 605                                 __asm__ __volatile__("sync");
 606
 607                                 /* disable injects */
 608                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 609                                 __asm__ __volatile__("sync");
 610                                 __asm__ __volatile__("isync");
 611
 612                                 /* re-initialize memory,
 613                                  * double word write the location again,
 614                                  * generates new ECC code this time */
 615                                 ppcDWstore((u32 *) i, writeback);
 616                                 __asm__ __volatile__("sync");
 617                         }
 618                         enable_interrupts();
 619                         return 0;
 620                 }
 621         }
 622         printf("Usage:\n%s\n", cmdtp->usage);
 623         return 1;
 624 }
 625
 626 U_BOOT_CMD(ecc, 4, 0, do_ecc,
 627            "ecc     - support for DDR ECC features\n",
 628            "status              - print out status info\n"
 629            "ecc captureclear        - clear capture regs data\n"
 630            "ecc sbecnt <val>        - set Single-Bit Error counter\n"
 631            "ecc sbethr <val>        - set Single-Bit Threshold\n"
 632            "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
 633            "  [-|+]sbe - Single-Bit Error\n"
 634            "  [-|+]mbe - Multiple-Bit Error\n"
 635            "  [-|+]mse - Memory Select Error\n"
 636            "  [-|+]all - all errors\n"
 637            "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
 638            "  mme - Multiple Memory Errors\n"
 639            "  sbe - Single-Bit Error\n"
 640            "  mbe - Multiple-Bit Error\n"
 641            "  mse - Memory Select Error\n"
 642            "  all - all errors\n"
 643            "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
 644            "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
 645            "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
 646            "ecc inject <en|dis>    - enable/disable error injection\n"
 647            "ecc mirror <en|dis>    - enable/disable mirror byte\n"
 648            "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
 649            "  - enables injects\n"
 650            "  - writes pattern injecting errors with double word access\n"
 651            "  - disables injects\n"
 652            "  - reads pattern back with double word access, generates error\n"
 653            "  - re-inits memory\n"
 654            "ecc testword <addr> <cnt>  - test mem region with word access:\n"
 655            "  - enables injects\n"
 656            "  - writes pattern injecting errors with word access\n"
 657            "  - writes pattern with word access, generates error\n"
 658            "  - disables injects\n" "  - re-inits memory");
 659 #endif                          /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
 660
 661 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 662 void
 663 ft_board_setup(void *blob, bd_t *bd)
 664 {
 665         u32 *p;
 666         int len;
 667
 668 #ifdef CONFIG_PCI
 669         ft_pci_setup(blob, bd);
 670 #endif
 671         ft_cpu_setup(blob, bd);
 672
 673         p = ft_get_prop(blob, "/memory/reg", &len);
 674         if (p != NULL) {
 675                 *p++ = cpu_to_be32(bd->bi_memstart);
 676                 *p = cpu_to_be32(bd->bi_memsize);
 677         }
 678 }
 679 #endif