board/mpc8360emds/mpc8360emds.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  * based on board/mpc8349emds/mpc8349emds.c
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  */
  15
  16 #include <common.h>
  17 #include <ioports.h>
  18 #include <mpc83xx.h>
  19 #include <i2c.h>
  20 #include <spd.h>
  21 #include <miiphy.h>
  22 #include <command.h>
  23 #if defined(CONFIG_PCI)
  24 #include <pci.h>
  25 #endif
  26 #if defined(CONFIG_SPD_EEPROM)
  27 #include <spd_sdram.h>
  28 #else
  29 #include <asm/mmu.h>
  30 #endif
  31
  32 const qe_iop_conf_t qe_iop_conf_tab[] = {
  33         /* GETH1 */
  34         {0,  3, 1, 0, 1}, /* TxD0 */
  35         {0,  4, 1, 0, 1}, /* TxD1 */
  36         {0,  5, 1, 0, 1}, /* TxD2 */
  37         {0,  6, 1, 0, 1}, /* TxD3 */
  38         {1,  6, 1, 0, 3}, /* TxD4 */
  39         {1,  7, 1, 0, 1}, /* TxD5 */
  40         {1,  9, 1, 0, 2}, /* TxD6 */
  41         {1, 10, 1, 0, 2}, /* TxD7 */
  42         {0,  9, 2, 0, 1}, /* RxD0 */
  43         {0, 10, 2, 0, 1}, /* RxD1 */
  44         {0, 11, 2, 0, 1}, /* RxD2 */
  45         {0, 12, 2, 0, 1}, /* RxD3 */
  46         {0, 13, 2, 0, 1}, /* RxD4 */
  47         {1,  1, 2, 0, 2}, /* RxD5 */
  48         {1,  0, 2, 0, 2}, /* RxD6 */
  49         {1,  4, 2, 0, 2}, /* RxD7 */
  50         {0,  7, 1, 0, 1}, /* TX_EN */
  51         {0,  8, 1, 0, 1}, /* TX_ER */
  52         {0, 15, 2, 0, 1}, /* RX_DV */
  53         {0, 16, 2, 0, 1}, /* RX_ER */
  54         {0,  0, 2, 0, 1}, /* RX_CLK */
  55         {2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
  56         {2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
  57         /* GETH2 */
  58         {0, 17, 1, 0, 1}, /* TxD0 */
  59         {0, 18, 1, 0, 1}, /* TxD1 */
  60         {0, 19, 1, 0, 1}, /* TxD2 */
  61         {0, 20, 1, 0, 1}, /* TxD3 */
  62         {1,  2, 1, 0, 1}, /* TxD4 */
  63         {1,  3, 1, 0, 2}, /* TxD5 */
  64         {1,  5, 1, 0, 3}, /* TxD6 */
  65         {1,  8, 1, 0, 3}, /* TxD7 */
  66         {0, 23, 2, 0, 1}, /* RxD0 */
  67         {0, 24, 2, 0, 1}, /* RxD1 */
  68         {0, 25, 2, 0, 1}, /* RxD2 */
  69         {0, 26, 2, 0, 1}, /* RxD3 */
  70         {0, 27, 2, 0, 1}, /* RxD4 */
  71         {1, 12, 2, 0, 2}, /* RxD5 */
  72         {1, 13, 2, 0, 3}, /* RxD6 */
  73         {1, 11, 2, 0, 2}, /* RxD7 */
  74         {0, 21, 1, 0, 1}, /* TX_EN */
  75         {0, 22, 1, 0, 1}, /* TX_ER */
  76         {0, 29, 2, 0, 1}, /* RX_DV */
  77         {0, 30, 2, 0, 1}, /* RX_ER */
  78         {0, 31, 2, 0, 1}, /* RX_CLK */
  79         {2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
  80         {2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
  81
  82         {0,  1, 3, 0, 2}, /* MDIO */
  83         {0,  2, 1, 0, 1}, /* MDC */
  84
  85         {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  86 };
  87
  88 int board_early_init_f(void)
  89 {
  90         volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
  91
  92         /* Enable flash write */
  93         bcsr[0xa] &= ~0x04;
  94
  95         return 0;
  96 }
  97
  98 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
  99 extern void ddr_enable_ecc(unsigned int dram_size);
 100 #endif
 101 int fixed_sdram(void);
 102 void sdram_init(void);
 103
 104 long int initdram(int board_type)
 105 {
 106         volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
 107         u32 msize = 0;
 108
 109         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 110                 return -1;
 111
 112         /* DDR SDRAM - Main SODIMM */
 113         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
 114 #if defined(CONFIG_SPD_EEPROM)
 115         msize = spd_sdram();
 116 #else
 117         msize = fixed_sdram();
 118 #endif
 119
 120 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 121         /*
 122          * Initialize DDR ECC byte
 123          */
 124         ddr_enable_ecc(msize * 1024 * 1024);
 125 #endif
 126         /*
 127          * Initialize SDRAM if it is on local bus.
 128          */
 129         sdram_init();
 130         puts("   DDR RAM: ");
 131         /* return total bus SDRAM size(bytes)  -- DDR */
 132         return (msize * 1024 * 1024);
 133 }
 134
 135 #if !defined(CONFIG_SPD_EEPROM)
 136 /*************************************************************************
 137  *  fixed sdram init -- doesn't use serial presence detect.
 138  ************************************************************************/
 139 int fixed_sdram(void)
 140 {
 141         volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
 142         u32 msize = 0;
 143         u32 ddr_size;
 144         u32 ddr_size_log2;
 145
 146         msize = CFG_DDR_SIZE;
 147         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 148              (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 149                 if (ddr_size & 1) {
 150                         return -1;
 151                 }
 152         }
 153         im->sysconf.ddrlaw[0].ar =
 154             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 155 #if (CFG_DDR_SIZE != 256)
 156 #warning Currenly any ddr size other than 256 is not supported
 157 #endif
 158         im->ddr.csbnds[0].csbnds = 0x00000007;
 159         im->ddr.csbnds[1].csbnds = 0x0008000f;
 160
 161         im->ddr.cs_config[0] = CFG_DDR_CONFIG;
 162         im->ddr.cs_config[1] = CFG_DDR_CONFIG;
 163
 164         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 165         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 166         im->ddr.sdram_cfg = CFG_DDR_CONTROL;
 167
 168         im->ddr.sdram_mode = CFG_DDR_MODE;
 169         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 170         udelay(200);
 171         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 172
 173         return msize;
 174 }
 175 #endif                          /*!CFG_SPD_EEPROM */
 176
 177 int checkboard(void)
 178 {
 179         puts("Board: Freescale MPC8360EMDS\n");
 180         return 0;
 181 }
 182
 183 /*
 184  * if MPC8360EMDS is soldered with SDRAM
 185  */
 186 #if defined(CFG_BR2_PRELIM)  \
 187         && defined(CFG_OR2_PRELIM) \
 188         && defined(CFG_LBLAWBAR2_PRELIM) \
 189         && defined(CFG_LBLAWAR2_PRELIM)
 190 /*
 191  * Initialize SDRAM memory on the Local Bus.
 192  */
 193
 194 void sdram_init(void)
 195 {
 196         volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
 197         volatile lbus83xx_t *lbc = &immap->lbus;
 198         uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
 199
 200         puts("\n   SDRAM on Local Bus: ");
 201         print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 202         /*
 203          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 204          */
 205         /*setup mtrpt, lsrt and lbcr for LB bus */
 206         lbc->lbcr = CFG_LBC_LBCR;
 207         lbc->mrtpr = CFG_LBC_MRTPR;
 208         lbc->lsrt = CFG_LBC_LSRT;
 209         asm("sync");
 210
 211         /*
 212          * Configure the SDRAM controller Machine Mode Register.
 213          */
 214         lbc->lsdmr = CFG_LBC_LSDMR_5;   /* Normal Operation */
 215         lbc->lsdmr = CFG_LBC_LSDMR_1;   /* Precharge All Banks */
 216         asm("sync");
 217         *sdram_addr = 0xff;
 218         udelay(100);
 219
 220         /*
 221          * We need do 8 times auto refresh operation.
 222          */
 223         lbc->lsdmr = CFG_LBC_LSDMR_2;
 224         asm("sync");
 225         *sdram_addr = 0xff;     /* 1 times */
 226         udelay(100);
 227         *sdram_addr = 0xff;     /* 2 times */
 228         udelay(100);
 229         *sdram_addr = 0xff;     /* 3 times */
 230         udelay(100);
 231         *sdram_addr = 0xff;     /* 4 times */
 232         udelay(100);
 233         *sdram_addr = 0xff;     /* 5 times */
 234         udelay(100);
 235         *sdram_addr = 0xff;     /* 6 times */
 236         udelay(100);
 237         *sdram_addr = 0xff;     /* 7 times */
 238         udelay(100);
 239         *sdram_addr = 0xff;     /* 8 times */
 240         udelay(100);
 241
 242         /* Mode register write operation */
 243         lbc->lsdmr = CFG_LBC_LSDMR_4;
 244         asm("sync");
 245         *(sdram_addr + 0xcc) = 0xff;
 246         udelay(100);
 247
 248         /* Normal operation */
 249         lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
 250         asm("sync");
 251         *sdram_addr = 0xff;
 252         udelay(100);
 253 }
 254 #else
 255 void sdram_init(void)
 256 {
 257         puts("SDRAM on Local Bus is NOT available!\n");
 258 }
 259 #endif
 260
 261 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 262 /*
 263  * ECC user commands
 264  */
 265 void ecc_print_status(void)
 266 {
 267         volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
 268         volatile ddr83xx_t *ddr = &immap->ddr;
 269
 270         printf("\nECC mode: %s\n\n",
 271                (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
 272
 273         /* Interrupts */
 274         printf("Memory Error Interrupt Enable:\n");
 275         printf("  Multiple-Bit Error Interrupt Enable: %d\n",
 276                (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
 277         printf("  Single-Bit Error Interrupt Enable: %d\n",
 278                (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
 279         printf("  Memory Select Error Interrupt Enable: %d\n\n",
 280                (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
 281
 282         /* Error disable */
 283         printf("Memory Error Disable:\n");
 284         printf("  Multiple-Bit Error Disable: %d\n",
 285                (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
 286         printf("  Sinle-Bit Error Disable: %d\n",
 287                (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
 288         printf("  Memory Select Error Disable: %d\n\n",
 289                (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
 290
 291         /* Error injection */
 292         printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
 293                ddr->data_err_inject_hi, ddr->data_err_inject_lo);
 294
 295         printf("Memory Data Path Error Injection Mask ECC:\n");
 296         printf("  ECC Mirror Byte: %d\n",
 297                (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
 298         printf("  ECC Injection Enable: %d\n",
 299                (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
 300         printf("  ECC Error Injection Mask: 0x%02x\n\n",
 301                ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
 302
 303         /* SBE counter/threshold */
 304         printf("Memory Single-Bit Error Management (0..255):\n");
 305         printf("  Single-Bit Error Threshold: %d\n",
 306                (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
 307         printf("  Single-Bit Error Counter: %d\n\n",
 308                (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
 309
 310         /* Error detect */
 311         printf("Memory Error Detect:\n");
 312         printf("  Multiple Memory Errors: %d\n",
 313                (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
 314         printf("  Multiple-Bit Error: %d\n",
 315                (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
 316         printf("  Single-Bit Error: %d\n",
 317                (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
 318         printf("  Memory Select Error: %d\n\n",
 319                (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
 320
 321         /* Capture data */
 322         printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
 323         printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
 324                ddr->capture_data_hi, ddr->capture_data_lo);
 325         printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
 326                ddr->capture_ecc & CAPTURE_ECC_ECE);
 327
 328         printf("Memory Error Attributes Capture:\n");
 329         printf(" Data Beat Number: %d\n",
 330                (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
 331                ECC_CAPT_ATTR_BNUM_SHIFT);
 332         printf("  Transaction Size: %d\n",
 333                (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
 334                ECC_CAPT_ATTR_TSIZ_SHIFT);
 335         printf("  Transaction Source: %d\n",
 336                (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
 337                ECC_CAPT_ATTR_TSRC_SHIFT);
 338         printf("  Transaction Type: %d\n",
 339                (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
 340                ECC_CAPT_ATTR_TTYP_SHIFT);
 341         printf("  Error Information Valid: %d\n\n",
 342                ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
 343 }
 344
 345 int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 346 {
 347         volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
 348         volatile ddr83xx_t *ddr = &immap->ddr;
 349         volatile u32 val;
 350         u64 *addr;
 351         u32 count;
 352         register u64 *i;
 353         u32 ret[2];
 354         u32 pattern[2];
 355         u32 writeback[2];
 356
 357         /* The pattern is written into memory to generate error */
 358         pattern[0] = 0xfedcba98UL;
 359         pattern[1] = 0x76543210UL;
 360
 361         /* After injecting error, re-initialize the memory with the value */
 362         writeback[0] = 0x01234567UL;
 363         writeback[1] = 0x89abcdefUL;
 364
 365         if (argc > 4) {
 366                 printf("Usage:\n%s\n", cmdtp->usage);
 367                 return 1;
 368         }
 369
 370         if (argc == 2) {
 371                 if (strcmp(argv[1], "status") == 0) {
 372                         ecc_print_status();
 373                         return 0;
 374                 } else if (strcmp(argv[1], "captureclear") == 0) {
 375                         ddr->capture_address = 0;
 376                         ddr->capture_data_hi = 0;
 377                         ddr->capture_data_lo = 0;
 378                         ddr->capture_ecc = 0;
 379                         ddr->capture_attributes = 0;
 380                         return 0;
 381                 }
 382         }
 383         if (argc == 3) {
 384                 if (strcmp(argv[1], "sbecnt") == 0) {
 385                         val = simple_strtoul(argv[2], NULL, 10);
 386                         if (val > 255) {
 387                                 printf("Incorrect Counter value, "
 388                                        "should be 0..255\n");
 389                                 return 1;
 390                         }
 391
 392                         val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
 393                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
 394
 395                         ddr->err_sbe = val;
 396                         return 0;
 397                 } else if (strcmp(argv[1], "sbethr") == 0) {
 398                         val = simple_strtoul(argv[2], NULL, 10);
 399                         if (val > 255) {
 400                                 printf("Incorrect Counter value, "
 401                                        "should be 0..255\n");
 402                                 return 1;
 403                         }
 404
 405                         val = (val << ECC_ERROR_MAN_SBET_SHIFT);
 406                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
 407
 408                         ddr->err_sbe = val;
 409                         return 0;
 410                 } else if (strcmp(argv[1], "errdisable") == 0) {
 411                         val = ddr->err_disable;
 412
 413                         if (strcmp(argv[2], "+sbe") == 0) {
 414                                 val |= ECC_ERROR_DISABLE_SBED;
 415                         } else if (strcmp(argv[2], "+mbe") == 0) {
 416                                 val |= ECC_ERROR_DISABLE_MBED;
 417                         } else if (strcmp(argv[2], "+mse") == 0) {
 418                                 val |= ECC_ERROR_DISABLE_MSED;
 419                         } else if (strcmp(argv[2], "+all") == 0) {
 420                                 val |= (ECC_ERROR_DISABLE_SBED |
 421                                         ECC_ERROR_DISABLE_MBED |
 422                                         ECC_ERROR_DISABLE_MSED);
 423                         } else if (strcmp(argv[2], "-sbe") == 0) {
 424                                 val &= ~ECC_ERROR_DISABLE_SBED;
 425                         } else if (strcmp(argv[2], "-mbe") == 0) {
 426                                 val &= ~ECC_ERROR_DISABLE_MBED;
 427                         } else if (strcmp(argv[2], "-mse") == 0) {
 428                                 val &= ~ECC_ERROR_DISABLE_MSED;
 429                         } else if (strcmp(argv[2], "-all") == 0) {
 430                                 val &= ~(ECC_ERROR_DISABLE_SBED |
 431                                          ECC_ERROR_DISABLE_MBED |
 432                                          ECC_ERROR_DISABLE_MSED);
 433                         } else {
 434                                 printf("Incorrect err_disable field\n");
 435                                 return 1;
 436                         }
 437
 438                         ddr->err_disable = val;
 439                         __asm__ __volatile__("sync");
 440                         __asm__ __volatile__("isync");
 441                         return 0;
 442                 } else if (strcmp(argv[1], "errdetectclr") == 0) {
 443                         val = ddr->err_detect;
 444
 445                         if (strcmp(argv[2], "mme") == 0) {
 446                                 val |= ECC_ERROR_DETECT_MME;
 447                         } else if (strcmp(argv[2], "sbe") == 0) {
 448                                 val |= ECC_ERROR_DETECT_SBE;
 449                         } else if (strcmp(argv[2], "mbe") == 0) {
 450                                 val |= ECC_ERROR_DETECT_MBE;
 451                         } else if (strcmp(argv[2], "mse") == 0) {
 452                                 val |= ECC_ERROR_DETECT_MSE;
 453                         } else if (strcmp(argv[2], "all") == 0) {
 454                                 val |= (ECC_ERROR_DETECT_MME |
 455                                         ECC_ERROR_DETECT_MBE |
 456                                         ECC_ERROR_DETECT_SBE |
 457                                         ECC_ERROR_DETECT_MSE);
 458                         } else {
 459                                 printf("Incorrect err_detect field\n");
 460                                 return 1;
 461                         }
 462
 463                         ddr->err_detect = val;
 464                         return 0;
 465                 } else if (strcmp(argv[1], "injectdatahi") == 0) {
 466                         val = simple_strtoul(argv[2], NULL, 16);
 467
 468                         ddr->data_err_inject_hi = val;
 469                         return 0;
 470                 } else if (strcmp(argv[1], "injectdatalo") == 0) {
 471                         val = simple_strtoul(argv[2], NULL, 16);
 472
 473                         ddr->data_err_inject_lo = val;
 474                         return 0;
 475                 } else if (strcmp(argv[1], "injectecc") == 0) {
 476                         val = simple_strtoul(argv[2], NULL, 16);
 477                         if (val > 0xff) {
 478                                 printf("Incorrect ECC inject mask, "
 479                                        "should be 0x00..0xff\n");
 480                                 return 1;
 481                         }
 482                         val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
 483
 484                         ddr->ecc_err_inject = val;
 485                         return 0;
 486                 } else if (strcmp(argv[1], "inject") == 0) {
 487                         val = ddr->ecc_err_inject;
 488
 489                         if (strcmp(argv[2], "en") == 0)
 490                                 val |= ECC_ERR_INJECT_EIEN;
 491                         else if (strcmp(argv[2], "dis") == 0)
 492                                 val &= ~ECC_ERR_INJECT_EIEN;
 493                         else
 494                                 printf("Incorrect command\n");
 495
 496                         ddr->ecc_err_inject = val;
 497                         __asm__ __volatile__("sync");
 498                         __asm__ __volatile__("isync");
 499                         return 0;
 500                 } else if (strcmp(argv[1], "mirror") == 0) {
 501                         val = ddr->ecc_err_inject;
 502
 503                         if (strcmp(argv[2], "en") == 0)
 504                                 val |= ECC_ERR_INJECT_EMB;
 505                         else if (strcmp(argv[2], "dis") == 0)
 506                                 val &= ~ECC_ERR_INJECT_EMB;
 507                         else
 508                                 printf("Incorrect command\n");
 509
 510                         ddr->ecc_err_inject = val;
 511                         return 0;
 512                 }
 513         }
 514         if (argc == 4) {
 515                 if (strcmp(argv[1], "testdw") == 0) {
 516                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 517                         count = simple_strtoul(argv[3], NULL, 16);
 518
 519                         if ((u32) addr % 8) {
 520                                 printf("Address not alligned on "
 521                                        "double word boundary\n");
 522                                 return 1;
 523                         }
 524                         disable_interrupts();
 525
 526                         for (i = addr; i < addr + count; i++) {
 527
 528                                 /* enable injects */
 529                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 530                                 __asm__ __volatile__("sync");
 531                                 __asm__ __volatile__("isync");
 532
 533                                 /* write memory location injecting errors */
 534                                 ppcDWstore((u32 *) i, pattern);
 535
 536                                 /* disable injects */
 537                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 538                                 __asm__ __volatile__("sync");
 539                                 __asm__ __volatile__("isync");
 540
 541                                 /* read data, this generates ECC error */
 542                                 ppcDWload((u32 *) i, ret);
 543
 544                                 /* re-initialize memory, double word write the location again,
 545                                  * generates new ECC code this time */
 546                                 ppcDWstore((u32 *) i, writeback);
 547                         }
 548                         enable_interrupts();
 549                         return 0;
 550                 }
 551                 if (strcmp(argv[1], "testword") == 0) {
 552                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 553                         count = simple_strtoul(argv[3], NULL, 16);
 554
 555                         if ((u32) addr % 8) {
 556                                 printf("Address not alligned on "
 557                                        "double word boundary\n");
 558                                 return 1;
 559                         }
 560                         disable_interrupts();
 561
 562                         for (i = addr; i < addr + count; i++) {
 563
 564                                 /* enable injects */
 565                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 566                                 __asm__ __volatile__("sync");
 567                                 __asm__ __volatile__("isync");
 568
 569                                 /* write memory location injecting errors */
 570                                 *(u32 *) i = 0xfedcba98UL;
 571                                 __asm__ __volatile__("sync");
 572
 573                                 /* sub double word write,
 574                                  * bus will read-modify-write,
 575                                  * generates ECC error */
 576                                 *((u32 *) i + 1) = 0x76543210UL;
 577                                 __asm__ __volatile__("sync");
 578
 579                                 /* disable injects */
 580                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 581                                 __asm__ __volatile__("sync");
 582                                 __asm__ __volatile__("isync");
 583
 584                                 /* re-initialize memory,
 585                                  * double word write the location again,
 586                                  * generates new ECC code this time */
 587                                 ppcDWstore((u32 *) i, writeback);
 588                         }
 589                         enable_interrupts();
 590                         return 0;
 591                 }
 592         }
 593         printf("Usage:\n%s\n", cmdtp->usage);
 594         return 1;
 595 }
 596
 597 U_BOOT_CMD(ecc, 4, 0, do_ecc,
 598            "ecc     - support for DDR ECC features\n",
 599            "status              - print out status info\n"
 600            "ecc captureclear        - clear capture regs data\n"
 601            "ecc sbecnt <val>        - set Single-Bit Error counter\n"
 602            "ecc sbethr <val>        - set Single-Bit Threshold\n"
 603            "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
 604            "  [-|+]sbe - Single-Bit Error\n"
 605            "  [-|+]mbe - Multiple-Bit Error\n"
 606            "  [-|+]mse - Memory Select Error\n"
 607            "  [-|+]all - all errors\n"
 608            "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
 609            "  mme - Multiple Memory Errors\n"
 610            "  sbe - Single-Bit Error\n"
 611            "  mbe - Multiple-Bit Error\n"
 612            "  mse - Memory Select Error\n"
 613            "  all - all errors\n"
 614            "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
 615            "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
 616            "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
 617            "ecc inject <en|dis>    - enable/disable error injection\n"
 618            "ecc mirror <en|dis>    - enable/disable mirror byte\n"
 619            "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
 620            "  - enables injects\n"
 621            "  - writes pattern injecting errors with double word access\n"
 622            "  - disables injects\n"
 623            "  - reads pattern back with double word access, generates error\n"
 624            "  - re-inits memory\n"
 625            "ecc testword <addr> <cnt>  - test mem region with word access:\n"
 626            "  - enables injects\n"
 627            "  - writes pattern injecting errors with word access\n"
 628            "  - writes pattern with word access, generates error\n"
 629            "  - disables injects\n" "  - re-inits memory");
 630 #endif                          /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */