board/mpc8360emds/mpc8360emds.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  * based on board/mpc8349emds/mpc8349emds.c
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  */
  15
  16 #include <common.h>
  17 #include <ioports.h>
  18 #include <mpc83xx.h>
  19 #include <i2c.h>
  20 #include <spd.h>
  21 #include <miiphy.h>
  22 #include <command.h>
  23 #if defined(CONFIG_PCI)
  24 #include <pci.h>
  25 #endif
  26 #if defined(CONFIG_SPD_EEPROM)
  27 #include <spd_sdram.h>
  28 #else
  29 #include <asm/mmu.h>
  30 #endif
  31 #if defined(CONFIG_OF_FLAT_TREE)
  32 #include <ft_build.h>
  33 #endif
  34
  35 const qe_iop_conf_t qe_iop_conf_tab[] = {
  36         /* GETH1 */
  37         {0,  3, 1, 0, 1}, /* TxD0 */
  38         {0,  4, 1, 0, 1}, /* TxD1 */
  39         {0,  5, 1, 0, 1}, /* TxD2 */
  40         {0,  6, 1, 0, 1}, /* TxD3 */
  41         {1,  6, 1, 0, 3}, /* TxD4 */
  42         {1,  7, 1, 0, 1}, /* TxD5 */
  43         {1,  9, 1, 0, 2}, /* TxD6 */
  44         {1, 10, 1, 0, 2}, /* TxD7 */
  45         {0,  9, 2, 0, 1}, /* RxD0 */
  46         {0, 10, 2, 0, 1}, /* RxD1 */
  47         {0, 11, 2, 0, 1}, /* RxD2 */
  48         {0, 12, 2, 0, 1}, /* RxD3 */
  49         {0, 13, 2, 0, 1}, /* RxD4 */
  50         {1,  1, 2, 0, 2}, /* RxD5 */
  51         {1,  0, 2, 0, 2}, /* RxD6 */
  52         {1,  4, 2, 0, 2}, /* RxD7 */
  53         {0,  7, 1, 0, 1}, /* TX_EN */
  54         {0,  8, 1, 0, 1}, /* TX_ER */
  55         {0, 15, 2, 0, 1}, /* RX_DV */
  56         {0, 16, 2, 0, 1}, /* RX_ER */
  57         {0,  0, 2, 0, 1}, /* RX_CLK */
  58         {2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
  59         {2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
  60         /* GETH2 */
  61         {0, 17, 1, 0, 1}, /* TxD0 */
  62         {0, 18, 1, 0, 1}, /* TxD1 */
  63         {0, 19, 1, 0, 1}, /* TxD2 */
  64         {0, 20, 1, 0, 1}, /* TxD3 */
  65         {1,  2, 1, 0, 1}, /* TxD4 */
  66         {1,  3, 1, 0, 2}, /* TxD5 */
  67         {1,  5, 1, 0, 3}, /* TxD6 */
  68         {1,  8, 1, 0, 3}, /* TxD7 */
  69         {0, 23, 2, 0, 1}, /* RxD0 */
  70         {0, 24, 2, 0, 1}, /* RxD1 */
  71         {0, 25, 2, 0, 1}, /* RxD2 */
  72         {0, 26, 2, 0, 1}, /* RxD3 */
  73         {0, 27, 2, 0, 1}, /* RxD4 */
  74         {1, 12, 2, 0, 2}, /* RxD5 */
  75         {1, 13, 2, 0, 3}, /* RxD6 */
  76         {1, 11, 2, 0, 2}, /* RxD7 */
  77         {0, 21, 1, 0, 1}, /* TX_EN */
  78         {0, 22, 1, 0, 1}, /* TX_ER */
  79         {0, 29, 2, 0, 1}, /* RX_DV */
  80         {0, 30, 2, 0, 1}, /* RX_ER */
  81         {0, 31, 2, 0, 1}, /* RX_CLK */
  82         {2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
  83         {2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
  84
  85         {0,  1, 3, 0, 2}, /* MDIO */
  86         {0,  2, 1, 0, 1}, /* MDC */
  87
  88         {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  89 };
  90
  91 int board_early_init_f(void)
  92 {
  93         volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
  94
  95         /* Enable flash write */
  96         bcsr[0xa] &= ~0x04;
  97
  98         return 0;
  99 }
 100
 101 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 102 extern void ddr_enable_ecc(unsigned int dram_size);
 103 #endif
 104 int fixed_sdram(void);
 105 void sdram_init(void);
 106
 107 long int initdram(int board_type)
 108 {
 109         volatile immap_t *im = (immap_t *) CFG_IMMR;
 110         u32 msize = 0;
 111
 112         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 113                 return -1;
 114
 115         /* DDR SDRAM - Main SODIMM */
 116         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
 117 #if defined(CONFIG_SPD_EEPROM)
 118         msize = spd_sdram();
 119 #else
 120         msize = fixed_sdram();
 121 #endif
 122
 123 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 124         /*
 125          * Initialize DDR ECC byte
 126          */
 127         ddr_enable_ecc(msize * 1024 * 1024);
 128 #endif
 129         /*
 130          * Initialize SDRAM if it is on local bus.
 131          */
 132         sdram_init();
 133         puts("   DDR RAM: ");
 134         /* return total bus SDRAM size(bytes)  -- DDR */
 135         return (msize * 1024 * 1024);
 136 }
 137
 138 #if !defined(CONFIG_SPD_EEPROM)
 139 /*************************************************************************
 140  *  fixed sdram init -- doesn't use serial presence detect.
 141  ************************************************************************/
 142 int fixed_sdram(void)
 143 {
 144         volatile immap_t *im = (immap_t *) CFG_IMMR;
 145         u32 msize = 0;
 146         u32 ddr_size;
 147         u32 ddr_size_log2;
 148
 149         msize = CFG_DDR_SIZE;
 150         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 151              (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 152                 if (ddr_size & 1) {
 153                         return -1;
 154                 }
 155         }
 156         im->sysconf.ddrlaw[0].ar =
 157             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 158 #if (CFG_DDR_SIZE != 256)
 159 #warning Currenly any ddr size other than 256 is not supported
 160 #endif
 161         im->ddr.csbnds[0].csbnds = 0x00000007;
 162         im->ddr.csbnds[1].csbnds = 0x0008000f;
 163
 164         im->ddr.cs_config[0] = CFG_DDR_CONFIG;
 165         im->ddr.cs_config[1] = CFG_DDR_CONFIG;
 166
 167         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 168         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 169         im->ddr.sdram_cfg = CFG_DDR_CONTROL;
 170
 171         im->ddr.sdram_mode = CFG_DDR_MODE;
 172         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 173         udelay(200);
 174         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 175
 176         return msize;
 177 }
 178 #endif                          /*!CFG_SPD_EEPROM */
 179
 180 int checkboard(void)
 181 {
 182         puts("Board: Freescale MPC8360EMDS\n");
 183         return 0;
 184 }
 185
 186 /*
 187  * if MPC8360EMDS is soldered with SDRAM
 188  */
 189 #if defined(CFG_BR2_PRELIM)  \
 190         && defined(CFG_OR2_PRELIM) \
 191         && defined(CFG_LBLAWBAR2_PRELIM) \
 192         && defined(CFG_LBLAWAR2_PRELIM)
 193 /*
 194  * Initialize SDRAM memory on the Local Bus.
 195  */
 196
 197 void sdram_init(void)
 198 {
 199         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 200         volatile lbus83xx_t *lbc = &immap->lbus;
 201         uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
 202
 203         puts("\n   SDRAM on Local Bus: ");
 204         print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 205         /*
 206          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 207          */
 208         /*setup mtrpt, lsrt and lbcr for LB bus */
 209         lbc->lbcr = CFG_LBC_LBCR;
 210         lbc->mrtpr = CFG_LBC_MRTPR;
 211         lbc->lsrt = CFG_LBC_LSRT;
 212         asm("sync");
 213
 214         /*
 215          * Configure the SDRAM controller Machine Mode Register.
 216          */
 217         lbc->lsdmr = CFG_LBC_LSDMR_5;   /* Normal Operation */
 218         lbc->lsdmr = CFG_LBC_LSDMR_1;   /* Precharge All Banks */
 219         asm("sync");
 220         *sdram_addr = 0xff;
 221         udelay(100);
 222
 223         /*
 224          * We need do 8 times auto refresh operation.
 225          */
 226         lbc->lsdmr = CFG_LBC_LSDMR_2;
 227         asm("sync");
 228         *sdram_addr = 0xff;     /* 1 times */
 229         udelay(100);
 230         *sdram_addr = 0xff;     /* 2 times */
 231         udelay(100);
 232         *sdram_addr = 0xff;     /* 3 times */
 233         udelay(100);
 234         *sdram_addr = 0xff;     /* 4 times */
 235         udelay(100);
 236         *sdram_addr = 0xff;     /* 5 times */
 237         udelay(100);
 238         *sdram_addr = 0xff;     /* 6 times */
 239         udelay(100);
 240         *sdram_addr = 0xff;     /* 7 times */
 241         udelay(100);
 242         *sdram_addr = 0xff;     /* 8 times */
 243         udelay(100);
 244
 245         /* Mode register write operation */
 246         lbc->lsdmr = CFG_LBC_LSDMR_4;
 247         asm("sync");
 248         *(sdram_addr + 0xcc) = 0xff;
 249         udelay(100);
 250
 251         /* Normal operation */
 252         lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
 253         asm("sync");
 254         *sdram_addr = 0xff;
 255         udelay(100);
 256 }
 257 #else
 258 void sdram_init(void)
 259 {
 260         puts("SDRAM on Local Bus is NOT available!\n");
 261 }
 262 #endif
 263
 264 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 265 /*
 266  * ECC user commands
 267  */
 268 void ecc_print_status(void)
 269 {
 270         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 271         volatile ddr83xx_t *ddr = &immap->ddr;
 272
 273         printf("\nECC mode: %s\n\n",
 274                (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
 275
 276         /* Interrupts */
 277         printf("Memory Error Interrupt Enable:\n");
 278         printf("  Multiple-Bit Error Interrupt Enable: %d\n",
 279                (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
 280         printf("  Single-Bit Error Interrupt Enable: %d\n",
 281                (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
 282         printf("  Memory Select Error Interrupt Enable: %d\n\n",
 283                (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
 284
 285         /* Error disable */
 286         printf("Memory Error Disable:\n");
 287         printf("  Multiple-Bit Error Disable: %d\n",
 288                (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
 289         printf("  Sinle-Bit Error Disable: %d\n",
 290                (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
 291         printf("  Memory Select Error Disable: %d\n\n",
 292                (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
 293
 294         /* Error injection */
 295         printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
 296                ddr->data_err_inject_hi, ddr->data_err_inject_lo);
 297
 298         printf("Memory Data Path Error Injection Mask ECC:\n");
 299         printf("  ECC Mirror Byte: %d\n",
 300                (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
 301         printf("  ECC Injection Enable: %d\n",
 302                (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
 303         printf("  ECC Error Injection Mask: 0x%02x\n\n",
 304                ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
 305
 306         /* SBE counter/threshold */
 307         printf("Memory Single-Bit Error Management (0..255):\n");
 308         printf("  Single-Bit Error Threshold: %d\n",
 309                (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
 310         printf("  Single-Bit Error Counter: %d\n\n",
 311                (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
 312
 313         /* Error detect */
 314         printf("Memory Error Detect:\n");
 315         printf("  Multiple Memory Errors: %d\n",
 316                (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
 317         printf("  Multiple-Bit Error: %d\n",
 318                (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
 319         printf("  Single-Bit Error: %d\n",
 320                (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
 321         printf("  Memory Select Error: %d\n\n",
 322                (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
 323
 324         /* Capture data */
 325         printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
 326         printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
 327                ddr->capture_data_hi, ddr->capture_data_lo);
 328         printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
 329                ddr->capture_ecc & CAPTURE_ECC_ECE);
 330
 331         printf("Memory Error Attributes Capture:\n");
 332         printf(" Data Beat Number: %d\n",
 333                (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
 334                ECC_CAPT_ATTR_BNUM_SHIFT);
 335         printf("  Transaction Size: %d\n",
 336                (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
 337                ECC_CAPT_ATTR_TSIZ_SHIFT);
 338         printf("  Transaction Source: %d\n",
 339                (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
 340                ECC_CAPT_ATTR_TSRC_SHIFT);
 341         printf("  Transaction Type: %d\n",
 342                (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
 343                ECC_CAPT_ATTR_TTYP_SHIFT);
 344         printf("  Error Information Valid: %d\n\n",
 345                ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
 346 }
 347
 348 int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 349 {
 350         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 351         volatile ddr83xx_t *ddr = &immap->ddr;
 352         volatile u32 val;
 353         u64 *addr;
 354         u32 count;
 355         register u64 *i;
 356         u32 ret[2];
 357         u32 pattern[2];
 358         u32 writeback[2];
 359
 360         /* The pattern is written into memory to generate error */
 361         pattern[0] = 0xfedcba98UL;
 362         pattern[1] = 0x76543210UL;
 363
 364         /* After injecting error, re-initialize the memory with the value */
 365         writeback[0] = 0x01234567UL;
 366         writeback[1] = 0x89abcdefUL;
 367
 368         if (argc > 4) {
 369                 printf("Usage:\n%s\n", cmdtp->usage);
 370                 return 1;
 371         }
 372
 373         if (argc == 2) {
 374                 if (strcmp(argv[1], "status") == 0) {
 375                         ecc_print_status();
 376                         return 0;
 377                 } else if (strcmp(argv[1], "captureclear") == 0) {
 378                         ddr->capture_address = 0;
 379                         ddr->capture_data_hi = 0;
 380                         ddr->capture_data_lo = 0;
 381                         ddr->capture_ecc = 0;
 382                         ddr->capture_attributes = 0;
 383                         return 0;
 384                 }
 385         }
 386         if (argc == 3) {
 387                 if (strcmp(argv[1], "sbecnt") == 0) {
 388                         val = simple_strtoul(argv[2], NULL, 10);
 389                         if (val > 255) {
 390                                 printf("Incorrect Counter value, "
 391                                        "should be 0..255\n");
 392                                 return 1;
 393                         }
 394
 395                         val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
 396                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
 397
 398                         ddr->err_sbe = val;
 399                         return 0;
 400                 } else if (strcmp(argv[1], "sbethr") == 0) {
 401                         val = simple_strtoul(argv[2], NULL, 10);
 402                         if (val > 255) {
 403                                 printf("Incorrect Counter value, "
 404                                        "should be 0..255\n");
 405                                 return 1;
 406                         }
 407
 408                         val = (val << ECC_ERROR_MAN_SBET_SHIFT);
 409                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
 410
 411                         ddr->err_sbe = val;
 412                         return 0;
 413                 } else if (strcmp(argv[1], "errdisable") == 0) {
 414                         val = ddr->err_disable;
 415
 416                         if (strcmp(argv[2], "+sbe") == 0) {
 417                                 val |= ECC_ERROR_DISABLE_SBED;
 418                         } else if (strcmp(argv[2], "+mbe") == 0) {
 419                                 val |= ECC_ERROR_DISABLE_MBED;
 420                         } else if (strcmp(argv[2], "+mse") == 0) {
 421                                 val |= ECC_ERROR_DISABLE_MSED;
 422                         } else if (strcmp(argv[2], "+all") == 0) {
 423                                 val |= (ECC_ERROR_DISABLE_SBED |
 424                                         ECC_ERROR_DISABLE_MBED |
 425                                         ECC_ERROR_DISABLE_MSED);
 426                         } else if (strcmp(argv[2], "-sbe") == 0) {
 427                                 val &= ~ECC_ERROR_DISABLE_SBED;
 428                         } else if (strcmp(argv[2], "-mbe") == 0) {
 429                                 val &= ~ECC_ERROR_DISABLE_MBED;
 430                         } else if (strcmp(argv[2], "-mse") == 0) {
 431                                 val &= ~ECC_ERROR_DISABLE_MSED;
 432                         } else if (strcmp(argv[2], "-all") == 0) {
 433                                 val &= ~(ECC_ERROR_DISABLE_SBED |
 434                                          ECC_ERROR_DISABLE_MBED |
 435                                          ECC_ERROR_DISABLE_MSED);
 436                         } else {
 437                                 printf("Incorrect err_disable field\n");
 438                                 return 1;
 439                         }
 440
 441                         ddr->err_disable = val;
 442                         __asm__ __volatile__("sync");
 443                         __asm__ __volatile__("isync");
 444                         return 0;
 445                 } else if (strcmp(argv[1], "errdetectclr") == 0) {
 446                         val = ddr->err_detect;
 447
 448                         if (strcmp(argv[2], "mme") == 0) {
 449                                 val |= ECC_ERROR_DETECT_MME;
 450                         } else if (strcmp(argv[2], "sbe") == 0) {
 451                                 val |= ECC_ERROR_DETECT_SBE;
 452                         } else if (strcmp(argv[2], "mbe") == 0) {
 453                                 val |= ECC_ERROR_DETECT_MBE;
 454                         } else if (strcmp(argv[2], "mse") == 0) {
 455                                 val |= ECC_ERROR_DETECT_MSE;
 456                         } else if (strcmp(argv[2], "all") == 0) {
 457                                 val |= (ECC_ERROR_DETECT_MME |
 458                                         ECC_ERROR_DETECT_MBE |
 459                                         ECC_ERROR_DETECT_SBE |
 460                                         ECC_ERROR_DETECT_MSE);
 461                         } else {
 462                                 printf("Incorrect err_detect field\n");
 463                                 return 1;
 464                         }
 465
 466                         ddr->err_detect = val;
 467                         return 0;
 468                 } else if (strcmp(argv[1], "injectdatahi") == 0) {
 469                         val = simple_strtoul(argv[2], NULL, 16);
 470
 471                         ddr->data_err_inject_hi = val;
 472                         return 0;
 473                 } else if (strcmp(argv[1], "injectdatalo") == 0) {
 474                         val = simple_strtoul(argv[2], NULL, 16);
 475
 476                         ddr->data_err_inject_lo = val;
 477                         return 0;
 478                 } else if (strcmp(argv[1], "injectecc") == 0) {
 479                         val = simple_strtoul(argv[2], NULL, 16);
 480                         if (val > 0xff) {
 481                                 printf("Incorrect ECC inject mask, "
 482                                        "should be 0x00..0xff\n");
 483                                 return 1;
 484                         }
 485                         val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
 486
 487                         ddr->ecc_err_inject = val;
 488                         return 0;
 489                 } else if (strcmp(argv[1], "inject") == 0) {
 490                         val = ddr->ecc_err_inject;
 491
 492                         if (strcmp(argv[2], "en") == 0)
 493                                 val |= ECC_ERR_INJECT_EIEN;
 494                         else if (strcmp(argv[2], "dis") == 0)
 495                                 val &= ~ECC_ERR_INJECT_EIEN;
 496                         else
 497                                 printf("Incorrect command\n");
 498
 499                         ddr->ecc_err_inject = val;
 500                         __asm__ __volatile__("sync");
 501                         __asm__ __volatile__("isync");
 502                         return 0;
 503                 } else if (strcmp(argv[1], "mirror") == 0) {
 504                         val = ddr->ecc_err_inject;
 505
 506                         if (strcmp(argv[2], "en") == 0)
 507                                 val |= ECC_ERR_INJECT_EMB;
 508                         else if (strcmp(argv[2], "dis") == 0)
 509                                 val &= ~ECC_ERR_INJECT_EMB;
 510                         else
 511                                 printf("Incorrect command\n");
 512
 513                         ddr->ecc_err_inject = val;
 514                         return 0;
 515                 }
 516         }
 517         if (argc == 4) {
 518                 if (strcmp(argv[1], "testdw") == 0) {
 519                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 520                         count = simple_strtoul(argv[3], NULL, 16);
 521
 522                         if ((u32) addr % 8) {
 523                                 printf("Address not alligned on "
 524                                        "double word boundary\n");
 525                                 return 1;
 526                         }
 527                         disable_interrupts();
 528
 529                         for (i = addr; i < addr + count; i++) {
 530
 531                                 /* enable injects */
 532                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 533                                 __asm__ __volatile__("sync");
 534                                 __asm__ __volatile__("isync");
 535
 536                                 /* write memory location injecting errors */
 537                                 ppcDWstore((u32 *) i, pattern);
 538                                 __asm__ __volatile__("sync");
 539
 540                                 /* disable injects */
 541                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 542                                 __asm__ __volatile__("sync");
 543                                 __asm__ __volatile__("isync");
 544
 545                                 /* read data, this generates ECC error */
 546                                 ppcDWload((u32 *) i, ret);
 547                                 __asm__ __volatile__("sync");
 548
 549                                 /* re-initialize memory, double word write the location again,
 550                                  * generates new ECC code this time */
 551                                 ppcDWstore((u32 *) i, writeback);
 552                                 __asm__ __volatile__("sync");
 553                         }
 554                         enable_interrupts();
 555                         return 0;
 556                 }
 557                 if (strcmp(argv[1], "testword") == 0) {
 558                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 559                         count = simple_strtoul(argv[3], NULL, 16);
 560
 561                         if ((u32) addr % 8) {
 562                                 printf("Address not alligned on "
 563                                        "double word boundary\n");
 564                                 return 1;
 565                         }
 566                         disable_interrupts();
 567
 568                         for (i = addr; i < addr + count; i++) {
 569
 570                                 /* enable injects */
 571                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 572                                 __asm__ __volatile__("sync");
 573                                 __asm__ __volatile__("isync");
 574
 575                                 /* write memory location injecting errors */
 576                                 *(u32 *) i = 0xfedcba98UL;
 577                                 __asm__ __volatile__("sync");
 578
 579                                 /* sub double word write,
 580                                  * bus will read-modify-write,
 581                                  * generates ECC error */
 582                                 *((u32 *) i + 1) = 0x76543210UL;
 583                                 __asm__ __volatile__("sync");
 584
 585                                 /* disable injects */
 586                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 587                                 __asm__ __volatile__("sync");
 588                                 __asm__ __volatile__("isync");
 589
 590                                 /* re-initialize memory,
 591                                  * double word write the location again,
 592                                  * generates new ECC code this time */
 593                                 ppcDWstore((u32 *) i, writeback);
 594                                 __asm__ __volatile__("sync");
 595                         }
 596                         enable_interrupts();
 597                         return 0;
 598                 }
 599         }
 600         printf("Usage:\n%s\n", cmdtp->usage);
 601         return 1;
 602 }
 603
 604 U_BOOT_CMD(ecc, 4, 0, do_ecc,
 605            "ecc     - support for DDR ECC features\n",
 606            "status              - print out status info\n"
 607            "ecc captureclear        - clear capture regs data\n"
 608            "ecc sbecnt <val>        - set Single-Bit Error counter\n"
 609            "ecc sbethr <val>        - set Single-Bit Threshold\n"
 610            "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
 611            "  [-|+]sbe - Single-Bit Error\n"
 612            "  [-|+]mbe - Multiple-Bit Error\n"
 613            "  [-|+]mse - Memory Select Error\n"
 614            "  [-|+]all - all errors\n"
 615            "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
 616            "  mme - Multiple Memory Errors\n"
 617            "  sbe - Single-Bit Error\n"
 618            "  mbe - Multiple-Bit Error\n"
 619            "  mse - Memory Select Error\n"
 620            "  all - all errors\n"
 621            "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
 622            "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
 623            "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
 624            "ecc inject <en|dis>    - enable/disable error injection\n"
 625            "ecc mirror <en|dis>    - enable/disable mirror byte\n"
 626            "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
 627            "  - enables injects\n"
 628            "  - writes pattern injecting errors with double word access\n"
 629            "  - disables injects\n"
 630            "  - reads pattern back with double word access, generates error\n"
 631            "  - re-inits memory\n"
 632            "ecc testword <addr> <cnt>  - test mem region with word access:\n"
 633            "  - enables injects\n"
 634            "  - writes pattern injecting errors with word access\n"
 635            "  - writes pattern with word access, generates error\n"
 636            "  - disables injects\n" "  - re-inits memory");
 637 #endif                          /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
 638
 639 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 640 void
 641 ft_board_setup(void *blob, bd_t *bd)
 642 {
 643         u32 *p;
 644         int len;
 645
 646 #ifdef CONFIG_PCI
 647         ft_pci_setup(blob, bd);
 648 #endif
 649         ft_cpu_setup(blob, bd);
 650
 651         p = ft_get_prop(blob, "/memory/reg", &len);
 652         if (p != NULL) {
 653                 *p++ = cpu_to_be32(bd->bi_memstart);
 654                 *p = cpu_to_be32(bd->bi_memsize);
 655         }
 656 }
 657 #endif