2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
20 #if defined(CONFIG_PCI)
23 #if defined(CONFIG_SPD_EEPROM)
24 #include <spd_sdram.h>
28 #if defined(CONFIG_OF_FLAT_TREE)
30 #elif defined(CONFIG_OF_LIBFDT)
32 #include <libfdt_env.h>
35 const qe_iop_conf_t qe_iop_conf_tab[] = {
37 {0, 3, 1, 0, 1}, /* TxD0 */
38 {0, 4, 1, 0, 1}, /* TxD1 */
39 {0, 5, 1, 0, 1}, /* TxD2 */
40 {0, 6, 1, 0, 1}, /* TxD3 */
41 {1, 6, 1, 0, 3}, /* TxD4 */
42 {1, 7, 1, 0, 1}, /* TxD5 */
43 {1, 9, 1, 0, 2}, /* TxD6 */
44 {1, 10, 1, 0, 2}, /* TxD7 */
45 {0, 9, 2, 0, 1}, /* RxD0 */
46 {0, 10, 2, 0, 1}, /* RxD1 */
47 {0, 11, 2, 0, 1}, /* RxD2 */
48 {0, 12, 2, 0, 1}, /* RxD3 */
49 {0, 13, 2, 0, 1}, /* RxD4 */
50 {1, 1, 2, 0, 2}, /* RxD5 */
51 {1, 0, 2, 0, 2}, /* RxD6 */
52 {1, 4, 2, 0, 2}, /* RxD7 */
53 {0, 7, 1, 0, 1}, /* TX_EN */
54 {0, 8, 1, 0, 1}, /* TX_ER */
55 {0, 15, 2, 0, 1}, /* RX_DV */
56 {0, 16, 2, 0, 1}, /* RX_ER */
57 {0, 0, 2, 0, 1}, /* RX_CLK */
58 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
59 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
61 {0, 17, 1, 0, 1}, /* TxD0 */
62 {0, 18, 1, 0, 1}, /* TxD1 */
63 {0, 19, 1, 0, 1}, /* TxD2 */
64 {0, 20, 1, 0, 1}, /* TxD3 */
65 {1, 2, 1, 0, 1}, /* TxD4 */
66 {1, 3, 1, 0, 2}, /* TxD5 */
67 {1, 5, 1, 0, 3}, /* TxD6 */
68 {1, 8, 1, 0, 3}, /* TxD7 */
69 {0, 23, 2, 0, 1}, /* RxD0 */
70 {0, 24, 2, 0, 1}, /* RxD1 */
71 {0, 25, 2, 0, 1}, /* RxD2 */
72 {0, 26, 2, 0, 1}, /* RxD3 */
73 {0, 27, 2, 0, 1}, /* RxD4 */
74 {1, 12, 2, 0, 2}, /* RxD5 */
75 {1, 13, 2, 0, 3}, /* RxD6 */
76 {1, 11, 2, 0, 2}, /* RxD7 */
77 {0, 21, 1, 0, 1}, /* TX_EN */
78 {0, 22, 1, 0, 1}, /* TX_ER */
79 {0, 29, 2, 0, 1}, /* RX_DV */
80 {0, 30, 2, 0, 1}, /* RX_ER */
81 {0, 31, 2, 0, 1}, /* RX_CLK */
82 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
83 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
85 {0, 1, 3, 0, 2}, /* MDIO */
86 {0, 2, 1, 0, 1}, /* MDC */
88 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
91 int board_early_init_f(void)
94 u8 *bcsr = (u8 *)CFG_BCSR;
95 const immap_t *immr = (immap_t *)CFG_IMMR;
97 /* Enable flash write */
100 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
101 if (immr->sysconf.spridr == SPR_8360_REV20 ||
102 immr->sysconf.spridr == SPR_8360E_REV20 ||
103 immr->sysconf.spridr == SPR_8360_REV21 ||
104 immr->sysconf.spridr == SPR_8360E_REV21)
110 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
111 extern void ddr_enable_ecc(unsigned int dram_size);
113 int fixed_sdram(void);
114 void sdram_init(void);
116 long int initdram(int board_type)
118 volatile immap_t *im = (immap_t *) CFG_IMMR;
121 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
124 /* DDR SDRAM - Main SODIMM */
125 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
126 #if defined(CONFIG_SPD_EEPROM)
129 msize = fixed_sdram();
132 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
134 * Initialize DDR ECC byte
136 ddr_enable_ecc(msize * 1024 * 1024);
139 * Initialize SDRAM if it is on local bus.
143 /* return total bus SDRAM size(bytes) -- DDR */
144 return (msize * 1024 * 1024);
147 #if !defined(CONFIG_SPD_EEPROM)
148 /*************************************************************************
149 * fixed sdram init -- doesn't use serial presence detect.
150 ************************************************************************/
151 int fixed_sdram(void)
153 volatile immap_t *im = (immap_t *) CFG_IMMR;
158 msize = CFG_DDR_SIZE;
159 for (ddr_size = msize << 20, ddr_size_log2 = 0;
160 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
165 im->sysconf.ddrlaw[0].ar =
166 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
167 #if (CFG_DDR_SIZE != 256)
168 #warning Currenly any ddr size other than 256 is not supported
171 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
172 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
173 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
174 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
175 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
176 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
177 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
178 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
179 im->ddr.sdram_mode = CFG_DDR_MODE;
180 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
181 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
182 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
184 im->ddr.csbnds[0].csbnds = 0x00000007;
185 im->ddr.csbnds[1].csbnds = 0x0008000f;
187 im->ddr.cs_config[0] = CFG_DDR_CONFIG;
188 im->ddr.cs_config[1] = CFG_DDR_CONFIG;
190 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
191 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
192 im->ddr.sdram_cfg = CFG_DDR_CONTROL;
194 im->ddr.sdram_mode = CFG_DDR_MODE;
195 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
198 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
202 #endif /*!CFG_SPD_EEPROM */
206 puts("Board: Freescale MPC8360EMDS\n");
211 * if MPC8360EMDS is soldered with SDRAM
213 #if defined(CFG_BR2_PRELIM) \
214 && defined(CFG_OR2_PRELIM) \
215 && defined(CFG_LBLAWBAR2_PRELIM) \
216 && defined(CFG_LBLAWAR2_PRELIM)
218 * Initialize SDRAM memory on the Local Bus.
221 void sdram_init(void)
223 volatile immap_t *immap = (immap_t *) CFG_IMMR;
224 volatile lbus83xx_t *lbc = &immap->lbus;
225 uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
227 puts("\n SDRAM on Local Bus: ");
228 print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
230 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
232 /*setup mtrpt, lsrt and lbcr for LB bus */
233 lbc->lbcr = CFG_LBC_LBCR;
234 lbc->mrtpr = CFG_LBC_MRTPR;
235 lbc->lsrt = CFG_LBC_LSRT;
239 * Configure the SDRAM controller Machine Mode Register.
241 lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */
242 lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */
248 * We need do 8 times auto refresh operation.
250 lbc->lsdmr = CFG_LBC_LSDMR_2;
252 *sdram_addr = 0xff; /* 1 times */
254 *sdram_addr = 0xff; /* 2 times */
256 *sdram_addr = 0xff; /* 3 times */
258 *sdram_addr = 0xff; /* 4 times */
260 *sdram_addr = 0xff; /* 5 times */
262 *sdram_addr = 0xff; /* 6 times */
264 *sdram_addr = 0xff; /* 7 times */
266 *sdram_addr = 0xff; /* 8 times */
269 /* Mode register write operation */
270 lbc->lsdmr = CFG_LBC_LSDMR_4;
272 *(sdram_addr + 0xcc) = 0xff;
275 /* Normal operation */
276 lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
282 void sdram_init(void)
284 puts("SDRAM on Local Bus is NOT available!\n");
288 #if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
289 && defined(CONFIG_OF_BOARD_SETUP)
292 * Prototypes of functions that we use.
294 void ft_cpu_setup(void *blob, bd_t *bd);
297 void ft_pci_setup(void *blob, bd_t *bd);
301 ft_board_setup(void *blob, bd_t *bd)
303 #if defined(CONFIG_OF_LIBFDT)
307 nodeoffset = fdt_find_node_by_path(blob, "/memory");
308 if (nodeoffset >= 0) {
309 tmp[0] = cpu_to_be32(bd->bi_memstart);
310 tmp[1] = cpu_to_be32(bd->bi_memsize);
311 fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
317 p = ft_get_prop(blob, "/memory/reg", &len);
319 *p++ = cpu_to_be32(bd->bi_memstart);
320 *p = cpu_to_be32(bd->bi_memsize);
325 ft_pci_setup(blob, bd);
327 ft_cpu_setup(blob, bd);
329 #endif /* CONFIG_OF_x */